SN74SSTVF16857 具有 SSTL_2 输入和输出的 14 位寄存缓冲器
This 14-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.
All inputs are SSTL_2, except the LVCMOS reset (RESET)\ input. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_2 Class I specifications.
The SN74SSTVF16857 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low.
The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset, and all outputs are forced low. The LVCMOS RESET\ input always must be held at a valid logic high or low level
| SN74SSTVF16857 | |
| Voltage Nodes(V) | 2.5 |
| Input Level | SSTL_2 |
| Output Level | SSTL_2 |
| Technology Family | SSTV |
| Rating | Catalog |
SN74SSTVF16857 特性
- Member of the Texas Instruments Widebus™ Family
- Operates at 2.3 V to 2.7 V for PC1600, PC2100, and PC2700; 2.5 V to 2.7 V for PC3200
- Pinout and Functionality Compatible With JEDEC Standard SSTV16857
- 600 ps Faster (Simultaneous Switching) Than JEDEC Standard SSTV16857 in PC2700 DIMM Applications
- Output Edge-Control Circuitry Minimizes Switching Noise in Unterminated DIMM Load
- Outputs Meet SSTL_2 Class I Specifications
- Supports SSTL_2 Data Inputs
- Differential Clock (CLK and CLK\) Inputs
- Supports LVCMOS Switching Levels on the RESET\ Input
- RESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low
- Flow-Through Architecture Optimizes PCB Layout
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
SN74SSTVF16857 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74SSTVF16857GR | ACTIVE | 0 to 70 | 2.10 | 1ku | TSSOP (DGG) | 48 | 2000 | LARGE T&R | |
| SN74SSTVF16857GRG4 | ACTIVE | 0 to 70 | 2.10 | 1ku | TSSOP (DGG) | 48 | 2000 | LARGE T&R | |
| SN74SSTVF16857VR | ACTIVE | 0 to 70 | 2.10 | 1ku | TVSOP (DGV) | 48 | 2000 | LARGE T&R | |
| SN74SSTVF16857VRG4 | ACTIVE | 0 to 70 | 2.10 | 1ku | TVSOP (DGV) | 48 | 2000 | LARGE T&R |
SN74SSTVF16857 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74SSTVF16857GR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-2-260C-1 YEAR | SN74SSTVF16857GR | SN74SSTVF16857GR |
| SN74SSTVF16857GRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-2-260C-1 YEAR | SN74SSTVF16857GRG4 | SN74SSTVF16857GRG4 |
| SN74SSTVF16857VR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74SSTVF16857VR | SN74SSTVF16857VR |
| SN74SSTVF16857VRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74SSTVF16857VRG4 | SN74SSTVF16857VRG4 |
SN74SSTVF16857 应用技术支持与电子电路设计开发资源下载
- SN74SSTVF16857 数据资料 dataSheet 下载.PDF
- TI 德州仪器特殊逻辑产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
