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LTC1750 - 14-Bit, 80Msps Wide Bandwidth ADC

The LTC®1750 is an 80Msps, 14-bit A/D converter designed for digitizing wide dynamic range signals up to frequencies of 500MHz. The input range of the ADC can be optimized with the on-chip PGA sample-and-hold circuit and flexible reference circuitry.

The LTC1750 has a highly linear sample-and-hold circuit with a bandwidth of 500MHz. The SFDR is 82dB with an input frequency of 250MHz. Ultralow jitter of 0.12psRMS allows undersampling of IF frequencies with minimal degradation in SNR. DC specs include ±3LSB INL and no missing codes.

The digital interface is compatible with 5V, 3V, 2V and LVDS logic systems. The ENC and ENC inputs may be driven differentially from PECL, GTL and other low swing logic families or from single-ended TTL or CMOS. The low noise, high gain ENC and ENC inputs may also be driven by a sinusoidal signal without degrading performance. A separate output power supply can be operated from 0.5V to 5V, making it easy to connect directly to any low voltage DSPs or FIFOs.

The 48-pin TSSOP package with a flow-through pinout simplifies the board layout.

特点 Sample Rate: 80Msps 500MHz Full Power Bandwidth S/H Direct IF Sampling Up to 500MHz PGA Front End (2.25VP-P or 1.35VP-P Input Range) 75.5dB SNR and 90dB SFDR (PGA = 0) 73dB SNR and 90dB SFDR (PGA = 1) No Missing Codes Single 5V Supply Power Dissipation: 1.45W Two Pin Selectable Reference Values Two’s Complement or Offset Binary Outputs Out-of-Range Indicator Data Ready Output Clock Pin-for-Pin Family 48-Pin TSSOP Package 典型应用

应用 Telecommunications Receivers Cellular Base Stations Spectrum Analysis Imaging Systems MRI Tomography 封装信息

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