74AUP2G34：双门
| Part Number | Data Sheet | SPICE Model | Number of Gates | Family | VCC Min (V) | VCC Max (V) | tpd max @ (1.5V) (ns) | tpd max @ (1.8V) (ns) | tpd max @ (2.5V) (ns) | tpd max @ (3.3V) (ns) | tpd max @ (5.0V) (ns) | Input/ Output Current |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP2G34 | 74AUP2G34.pdf | - | 2 | AUP | 0.8 | 3.6 | 10.3 | 8.1 | 6.4 | 5.6 | - | 4 |
Description
The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP2G34 is a dual buffer gate with standard push-pull outputs designed for operation over a power supply range of 0.8V to 3.6V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down.
Application
- Suited for battery and low power needs
- Wide array of products such as:
订购型号
- 74AUP2G3404FW3-7
- 74AUP2G3404FW4-7
- 74AUP2G34DW-7
- 74AUP2G34FW3-7
- 74AUP2G34FW4-7
SOT363
X2-DFN1010-6
X2-DFN1410-6
X2-DFN0910-6
- 74AUP2G34.pdf 74AUP2G34
- 74LVC2G34 dual buffer 74LVC2G34
- 74LVC2G34 dual buffer 74LVC2G34
