Part Number | Data Sheet | SPICE Model | Number of Gates | Family | VCC Min (V) | VCC Max (V) | tpd max @ (1.5V) (ns) | tpd max @ (1.8V) (ns) | tpd max @ (2.5V) (ns) | tpd max @ (3.3V) (ns) | tpd max @ (5.0V) (ns) | Input/ Output Current |
---|---|---|---|---|---|---|---|---|---|---|---|---|
74AUP2G86 | 74AUP2G86.pdf | - | 2 | AUP | 0.8 | 3.6 | 12.5 | 9.8 | 7.6 | 7.1 | - | 4 |
The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP2G86 is a dual two input EXCLUSIVE OR gate. Both gates have push-pull outputs designed for operation over a power supply range of 0.8 V to 3.6 V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down.