74HCT595：标准逻辑
| Part Number | Data Sheet | SPICE Model | Number of Gates | Family | VCC Min (V) | VCC Max (V) | tpd max @ (1.5V) (ns) | tpd max @ (1.8V) (ns) | tpd max @ (2.5V) (ns) | tpd max @ (3.3V) (ns) | tpd max @ (5.0V) (ns) | Input/ Output Current |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74HCT595 | 74HCT595.pdf | - | 0 | HCT | 4.5 | 5.5 | - | - | - | - | 50 | 4 |
Description
The 74HCT595 is an high speed CMOS device that is designed to be pin compatable with 74LS low power Schottky types. An eight bit shift register accpets data from the serial input (DS) on each positive transition of the shift register clock (STCP). When asserted low the reset function ( ) sets all shift register values to zero and is indepent of all clocks. Data from the input serial shift register is placed in the output register with a rising pulse on the storages resister clock (SHCP). With the output enable asserted low the 3-state outputs Q0-Q7 become active and present th All registers capture data on rising edge and change output on the falling edge. If both clocks are connected together the input shift register is always one clock cycle ahead of the output register.
Application
- General Purpose Logic
- Serial to Parallel Data conversion
- Capture and hold data for extended periods of time.
- Allow simple serial bit streams from a microcontroller to control as many peripheral lines as needed.
- Wide array of products such as:
- Computer peripherals
- Appliances
- Industrial control
订购型号
- 74HCT595S16-13
- 74HCT595T16-13
SO-16
TSSOP-16
- 74HCT595.pdf 74HCT595
