74LV00A：标准逻辑
| Part Number | Data Sheet | SPICE Model | Number of Gates | Family | VCC Min (V) | VCC Max (V) | tpd max @ (1.5V) (ns) | tpd max @ (1.8V) (ns) | tpd max @ (2.5V) (ns) | tpd max @ (3.3V) (ns) | tpd max @ (5.0V) (ns) | Input/ Output Current |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LV00A | 74LV00A.pdf | - | 4 | LV | 2 | 5.5 | - | - | 16.6 | 11.4 | 7.5 | 12 |
Description
The 74LV00A provides provides four independent 2-input NAND gates with standard push-pull outputs. The device is designed for operation with a power supply range of 2.0V to 5.5V.
The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down.
Application
- General Purpose Logic
- Power Down Signal Isolation
- Wide array of products such as:
- PCs, networking, notebooks, ultrabooks, netbooks
- Computer peripherals, hard drives, CD/DVD ROM
- TV, DVD, DVR, set top box
订购型号
- 74LV00AS14-13
- 74LV00AT14-13
TSSOP-14
SO-14
- 74LV00A.pdf 74LV00A
