74LVC240A：标准逻辑 _ BDTIC 中国领先电子元器件代理商

74LVC240A：标准逻辑

Part Number	Data Sheet	SPICE Model	Number of Gates	Family	VCC Min (V)	VCC Max (V)	tpd max @ (1.5V) (ns)	tpd max @ (1.8V) (ns)	tpd max @ (2.5V) (ns)	tpd max @ (3.3V) (ns)	tpd max @ (5.0V) (ns)	Input/ Output Current
74LVC240A	74LVC240A.pdf	-	8	LVC	1.65	3.6	-	12.7	8.3	6.3	-	24

Description

The 74LVC240A provides two 4-bit buffers/drivers with separate output-enable (OE) inputs. When OE is low, the device passes data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.

The device is designed for operation with a power supply range of 1.65V to 3.6V.

The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output preventing damaging current backflow when the device is powered down.

Application

General Purpose Logic
Bus Driving
Power Down Signal Isolation
Wide Array of Products Such as:
- PCs, Notebooks, Netbooks, Ultrabooks
- Networking Computer Peripherals, Hard Drives, CD/DVD ROM
- TV, DVD, DVR, Set Top Box

Features

Supply Voltage Range from 1.65V to 3.6V
Sinks or Sources 24 ma at VCC = 3V
CMOS Low Power Consumption
IOFF Supports Partial -Power Down Operation
Inputs or Outputs Accept up to 5.5V
Inputs Can Be Driven by 3.3V or 5V Allowing for Mixed Voltage Applications
Schmitt Trigger Action at All Inputs
Typical VOLP (Quiet Output Ground Bounce) Less than 0.8V with VCC = 3.3V and TA = +25°C
Typical VOHV (Quiet Output dynamic VOH) Greater than 2.0V with VCC = 3.3V and TA = +25°C
ESD Protection Tested per JESD 22
- Exceeds 200-V Machine Model (A115)
- Exceeds 2000-V Human Body Model (A114)
- Exceeds 1000-V Charged Device Model (C101)
Latch-Up Exceeds 250mA per JESD 78, Class I
All devices are:
- Totally Lead-Free & Fully RoHS compliant
- Halogen and Antimony Free.“Green” Device