74LVC2G38：双门
| Part Number | Data Sheet | SPICE Model | Number of Gates | Family | VCC Min (V) | VCC Max (V) | tpd max @ (1.5V) (ns) | tpd max @ (1.8V) (ns) | tpd max @ (2.5V) (ns) | tpd max @ (3.3V) (ns) | tpd max @ (5.0V) (ns) | Input/ Output Current |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74LVC2G38 | 74LVC2G38.pdf | - | 2 | LVC | 1.65 | 5.5 | - | 8.6 | 4.8 | 4.1 | 3.3 | 32 |
Description
The 74LVC2G38 is a dual two input NAND buffer gate with open-drain outputs. Both gates have push-pull outputs designed for operation over a power supply range of 1.65V to 5.5V. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down.
Application
- General Purpose Logic
- Power Down Signal Isolation
- Wide array of products such as:
- PCs, networking, notebooks, netbooks, PDAs
- Tablet Computers, E-readers
- Computer peripherals, hard drives, CD/DVD ROM
- TV, DVD, DVR, set top box
- Cell Phones, Personal Navigation / GPS
- MP3 players ,Cameras, Video Recorders
Features
- Wide Supply Voltage Range from 1.65 to 5.5V
- ± 24mA Output Drive at 3.3V
- CMOS low power consumption
- IOFF Supports Partial-Power-Down Mode Operation
- Inputs accept up to 5.5V
- Schmitt Trigger Action at all inputs make the circuit tolerant for slower input rise and fall time. The hysteresis is typically 65 mV at VCC = 3.0V
- ESD Protection Exceeds JESD 22
- 2000-V Human Body Model (A114)
- Exceeds 1000-V Charged Device Model (C101)
- Latch-Up Exceeds 70mA per JESD 78, Class I
- Leadless Packages Named per JESD30E
- Totally Lead-Free & Fully RoHS Compliant
- Halogen and Antimony Free. “Green” Device
X2-DFN1210-8
X2-DFN2010-8
X2-DFN1410-8
- 74LVC2G38.pdf 74LVC2G38
