Part Number | Data Sheet | SPICE Model | Number of Gates | Family | VCC Min (V) | VCC Max (V) | tpd max @ (1.5V) (ns) | tpd max @ (1.8V) (ns) | tpd max @ (2.5V) (ns) | tpd max @ (3.3V) (ns) | tpd max @ (5.0V) (ns) | Input/ Output Current |
---|---|---|---|---|---|---|---|---|---|---|---|---|
74LVC574A | 74LVC574A.pdf | - | 8 | LVC | 1.65 | 3.6 | - | 13.5 | 9 | 7 | - | 24 |
The 74LVC574A provides eight edge-triggered D-type flip-flops featuring 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing buffer registers, input/output (I/O) ports, bidirectional bus drivers, and working registers. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels set up at the data (D) inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.
These devices feature inputs and outputs on opposite sides of the package that facilitate printed circuit board layout.
The device is designed for operation with a power supply range of 1.65V to 3.6V. The device is fully specified for partial power down applications using IOFF.