产品特性

• Up to 40MIPS operation (at 3.0-3.6V)
• Industrial temperature range (-40°C to +85°C)
• Extended temperature range (-40°C to +125°C)
• High temperature range (-40°C to +150°C)
• Modified Harvard architecture
• C compiler optimized instruction set
• 16-bit wide data path
• 24-bit wide instructions
• Linear program memory addressing up to 4M instruction words
• Linear data memory addressing up to 64 Kbytes
• 83 base instructions: mostly 1 word/1 cycle
• Sixteen 16-bit General Purpose Registers
• Two 40-bit accumulators: With rounding and saturation options
• With rounding and saturation options
• Flexible and powerful addressing modes: Indirect, Modulo and Bit-Reversed
• Indirect, Modulo and Bit-Reversed
• Software stack
• 16 x 16 fractional/integer multiply operations
• 32/16 and 16/16 divide operations
• Single-cycle multiply and accumulate: Accumulator write back for DSP operations Dual data fetch
• Accumulator write back for DSP operations
• Dual data fetch
• Up to ±16-bit shifts for up to 40-bit data
• 8-channel hardware DMA:
• 2 Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA: Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing)
• Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing)
• Most peripherals support DMA
• 5-cycle latency
• 118 interrupt vectors
• Up to 67 available interrupt sources
• Up to 5 external interrupts
• 7 programmable priority levels
• 5 processor exceptions
• Wake-up/Interrupt-on-Change on up to 24 pins
• Output pins can drive from 3.0V to 3.6V
• All digital input pins are 5V tolerant
• 4 mA sink on all I/O pins
• Flexible clock options: External, crystal, resonator, internal RC Fully integrated PLL Extremely low jitter PLL
• External, crystal, resonator, internal RC
• Fully integrated PLL
• Extremely low jitter PLL

技术参数