74LVT573BQ: 3.3 V八进制D型透明锁存器;3态

74LVT573是高性能BiCMOS产品,设计用于3.3 V的VCC操作。该器件是八进制透明锁存器,耦合到八个3态输出缓冲器。该器件的这两个部分由锁存使能(LE)和输出使能(OE)控制门独立控制。74LVT573具有宽边针脚配置,可方便PC板布局并实现与微处理器的轻松接合。

锁存使能(LE)输入为高电平时,Dn输入上的数据会被传输到锁存输出。锁存器在LE为高电平时保持对数据输入的穿透,并存储使能从高电平跃迁至低电平前的一个设置时间存出现的数据。

3态输出缓冲器设计用于驱动高负载3态总线、MOS存储器或MOS微处理器。每个低电平有效输出使能(OE)都控制独立于锁存器操作的所有八个3态缓冲器。

OE为低电平时,锁存或穿透数据出现在输出处。OE为高电平时,输出处于高阻抗“关断”状态,这意味着它们既不驱动也不加载总线。

74LVT573BQ: 产品结构框图
74LVT573BQ: 应用结构框图
74LVT573BQ: 应用结构框图
74LVT573BQ: 应用结构框图
74LVT573BQ: 应用结构框图
Outline 3d SOT764-1
数据手册 (1)
名称/描述Modified Date
3.3 V octal D-type transparent latch; 3-state (REV 8.0) PDF (317.0 kB) 74LVT573 [English]15 Dec 2011
应用说明 (8)
名称/描述Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]13 Mar 2013
A metastability primer (REV 1.0) PDF (40.0 kB) AN219 [English]13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]13 Mar 2013
Test Fixtures for High Speed Logic (REV 1.0) PDF (341.0 kB) AN203 [English]02 Apr 1998
Transmission Lines and Terminations with Philips Advanced Logic Families (REV 1.0) PDF (217.0 kB) AN246 [English]01 Feb 1998
LVT (Low Voltage Technology) and ALVT (Advanced LVT) (REV 1.0) PDF (133.0 kB) AN243 [English]01 Jan 1998
选型工具指南 (2)
名称/描述Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]08 Jan 2015
封装信息 (1)
名称/描述Modified Date
plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x... (REV 1.0) PDF (190.0 kB) SOT764-1 [English]08 Feb 2016
包装 (1)
名称/描述Modified Date
DHVQFN20; Reel pack; SMD, 7" Q1/T1 Standard product orientation Orderable part number ending ,115 or... (REV 4.0) PDF (203.0 kB) SOT764-1_115 [English]23 Apr 2013
IBIS
SPICE
订购信息
型号状态FamilyVCC (V)功能Logic switching levels说明Output drive capability (mA)Package versiontpd (ns)No of bitsPower dissipation considerationsTamb (Cel)Rth(j-a) (K/W)Ψth(j-top) (K/W)Rth(j-c) (K/W)Package nameNo of pins
74LVT573BQActiveLVT2.7 - 3.6Latches/registered driversTTLoctal D-type transparent latch (3-state)-32/+64SOT764-12.78medium-40~85778.649DHVQFN2020
封装环保信息
产品编号封装说明Outline Version回流/波峰焊接包装产品状态部件编号订购码 (12NC)Marking化学成分RoHS / 无铅 / RHF无铅转换日期EFRIFR(FIT)MTBF(小时)MSLMSL LF
74LVT573BQSOT764-1Reel 7" Q1/T1Active74LVT573BQ,115 (9352 856 07115)LVT573BQ74LVT573BQAlways Pb-free70.81.337.52E811
3.3 V octal D-type transparent latch; 3-state 74LVT573PW
Sorting through the low voltage logic maze 74LVC_H_245A_Q100
Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
A metastability primer 74AHC573PW
Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100
Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100
Test Fixtures for High Speed Logic 74ABTH162245ADL
Transmission Lines and Terminations with Philips Advanced Logic Families 74LVTN16245BDGG
LVT (Low Voltage Technology) and ALVT (Advanced LVT) 74LVTN16245BDGG
ロジック製品セレクションガイド... 74LVC_H_245A_Q100
Logic selection guide 2016 74LVC_H_245A_Q100
lvt573 IBIS model 74LVT573PW
lvt Spice model 74LVT640PW
plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x... 74LVC_H_245A_Q100
DHVQFN20; Reel pack; SMD, 7" Q1/T1 Standard product orientation Orderable part number ending ,115 or... 74LVC_H_245A_Q100
74LVT573
74LVT573
74LVT573
74AVCM162836DGG
74LVT573
74VHC_T_245