The 74LVT573 is a high-performance BiCMOS product designed for VCC operation at 3.3 V. This device is an octal transparent latch coupled to eight 3-state output buffers. The two sections of the device are controlled independently by Latch Enable (LE) and Output Enable (OE) control gates. The 74LVT573 has a broadside pinout configuration to facilitate PC board layout and allow easy interface with microprocessors.
The data on the Dn inputs are transferred to the latch outputs when the Latch Enable (LE) input is High. The latch remains transparent to the data inputs while LE is High, and stores the data that is present one setup time before the High-to-Low enable transition.
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS memories, or MOS microprocessors. The active-Low Output Enable (OE) controls all eight 3-state buffers independent of the latch operation.
When OE is Low, the latched or transparent data appears at the outputs. When OE is High, the outputs are in the High-impedance “OFF” state, which means they will neither drive nor load the bus.
Name/Description | Modified Date |
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3.3 V octal D-type transparent latch; 3-state (REV 8.0) PDF (317.0 kB) 74LVT573 [English] | 15 Dec 2011 |
Name/Description | Modified Date |
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Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English] | 13 Mar 2013 |
A metastability primer (REV 1.0) PDF (40.0 kB) AN219 [English] | 13 Mar 2013 |
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English] | 13 Mar 2013 |
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English] | 13 Mar 2013 |
Test Fixtures for High Speed Logic (REV 1.0) PDF (341.0 kB) AN203 [English] | 02 Apr 1998 |
Transmission Lines and Terminations with Philips Advanced Logic Families (REV 1.0) PDF (217.0 kB) AN246 [English] | 01 Feb 1998 |
LVT (Low Voltage Technology) and ALVT (Advanced LVT) (REV 1.0) PDF (133.0 kB) AN243 [English] | 01 Jan 1998 |
Name/Description | Modified Date |
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ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
Name/Description | Modified Date |
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plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x... (REV 1.0) PDF (190.0 kB) SOT764-1 [English] | 08 Feb 2016 |
Name/Description | Modified Date |
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DHVQFN20; Reel pack; SMD, 7" Q1/T1 Standard product orientation Orderable part number ending ,115 or... (REV 4.0) PDF (203.0 kB) SOT764-1_115 [English] | 23 Apr 2013 |
Product | Status | Family | VCC (V) | Function | Description | Logic switching levels | Package version | Output drive capability (mA) | tpd (ns) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
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74LVT573BQ | Active | LVT | 2.7 - 3.6 | Latches/registered drivers | octal D-type transparent latch (3-state) | TTL | SOT764-1 | -32/+64 | 2.7 | 8 | medium | -40~85 | 77 | 8.6 | 49 | DHVQFN20 | 20 |
Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
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74LVT573BQ | SOT764-1 | Reel 7" Q1/T1 | Active | 74LVT573BQ,115 (9352 856 07115) | LVT573BQ | 74LVT573BQ | Always Pb-free | 70.8 | 1.33 | 7.52E8 | 1 | 1 |