MAC57D5xx MCU系列是一个多核架构解决方案,适用于中档仪表板和工业应用。这款MCU基于适合实时应用的ARM® Cortex®-M处理器,以及适合应用和人机接口的ARM® Cortex®-A处理器,提供最前沿的性能和稳定性。
MAC57D5xx MCU最多支持两个WVGA分辨率显示屏,包括一个带内联平视显示器硬件曲面的显示屏。图形内容可采用强大的Vivante 2D GPU和2D动画和合成引擎来生成,从而降低了内容创建的内存占用,集成步进电机驱动器和强大的I/O处理器。
MAC57D5xx MCU集成了恩智浦最新的SHE合规CSE2引擎,并能够满足ISO26262 ASIL-B功能安全合规性的要求。
名称/描述 | 类型 | 修改日期 |
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MAC57D5xx - Fact Sheet (REV 3) PDF (250.2 kB) MAC57D5XXFS | 简介 | 08 Aug 2016 |
QuadSPI Flash Controller utilizing the new Centered Read Strobe feature: An improved and simplified interface protocol... (REV 1) PDF (390.7 kB) CRSWP | 白皮书 | 18 Mar 2015 |
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SAC57D54H Data Sheet (REV 5) PDF (1.3 MB) SAC57D54H | 17 May 2016 |
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AN5285: MAC57D5xx Start-Up Sequence - Application notes (REV 0) PDF (324.5 kB) AN5285 | 02 May 2016 |
AN5265, MAC57D5xx Hardware Design Guidelines - Application note (REV 0) PDF (1.0 MB) AN5265 | 28 Apr 2016 |
AN5072, Introduction to Embedded Graphics with NXP® Devices-Application Notes (REV 0) PDF (796.7 kB) AN5072 | 09 Feb 2015 |
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SAC57D54H Reference Manual (REV 4.2) PDF (19.9 MB) SAC57D54HRM | 18 May 2016 |
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MAC57D5xxUG, MAC57D5xx Customer Evaluation Boards (REV 0) PDF (1.4 MB) MAC57D5XXUG | 04 May 2016 |
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EB833: MAC57D5xx STCU BIST Configuration (REV 0) PDF (295.6 kB) EB833 | 20 Mar 2016 |
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MAC57D5xx - Fact Sheet (REV 3) PDF (250.2 kB) MAC57D5XXFS | 08 Aug 2016 |
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QuadSPI Flash Controller utilizing the new Centered Read Strobe feature: An improved and simplified interface protocol... (REV 1) PDF (390.7 kB) CRSWP | 18 Mar 2015 |
型号 | 状态 | 状态 | 封装类型和焊端数 | Core Type | 工作频率 (Max) (MHz) | L1 Cache | 内部RAM (KB) | 内部闪存 (KB) | CAN | I2C | SPI | LinFlex D | Memory / Peripheral Protection | eDMA | 支持外部存储器 | 视频/显示功能 | Timer/PWM |
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SAC57D54HCVMO | Active | MAPBGA 516 | ARM Cortex-M4, ARM Cortex-M0+ IOP, ARM Cortex-A5 | 320 | 32/32 on A5 | 1300 | 4000 | 3 | 2 | 5 | 3 | Yes | 2x 16ch | 32-Bit DDR2 DRAM (320mhz), 16-Bit SDR DRAM (160mhz), 2x Dual DDR QuadSPI | 2x 2D-ACE, HUD Warping Engine, Video Input Unit, Segment LCD, OpenVG 1.1 | 8ch PIT, 3x SWT, ARTC, 4x 8ch Flextimer | |
SAC57D53MCVLT | Active | LQFP 208 | ARM Cortex-A5, ARM Cortex-M0+ IOP, ARM Cortex-M4 | 320 | 32/32 on A5 | 1300 | 3000 | 3 | 2 | 5 | 3 | Yes | 2x 16ch | 2x Dual DDR QuadSPI, 16-Bit SDR DRAM (160mhz), 32-Bit DDR2 DRAM (320mhz) | OpenVG 1.1, Segment LCD, 2x 2D-ACE, HUD Warping Engine, Video Input Unit | 8ch PIT, 3x SWT, ARTC, 4x 8ch Flextimer | |
SAC57D54HCVLT | Active | LQFP 208 | ARM Cortex-A5, ARM Cortex-M0+ IOP, ARM Cortex-M4 | 320 | 32/32 on A5 | 1300 | 4000 | 3 | 2 | 5 | 3 | Yes | 2x 16ch | 2x Dual DDR QuadSPI, 16-Bit SDR DRAM (160mhz), 32-Bit DDR2 DRAM (320mhz) | OpenVG 1.1, Segment LCD, 2x 2D-ACE, HUD Warping Engine, Video Input Unit | 8ch PIT, 3x SWT, ARTC, 4x 8ch Flextimer | |
SAC57D53MCVMO | Active | MAPBGA 516 | ARM Cortex-A5, ARM Cortex-M0+ IOP, ARM Cortex-M4 | 320 | 32/32 on A5 | 1300 | 3000 | 3 | 2 | 5 | 3 | Yes | 2x 16ch | 2x Dual DDR QuadSPI, 16-Bit SDR DRAM (160mhz), 32-Bit DDR2 DRAM (320mhz) | OpenVG 1.1, Segment LCD, 2x 2D-ACE, HUD Warping Engine, Video Input Unit | 8ch PIT, 3x SWT, ARTC, 4x 8ch Flextimer | |
SAC57D52LCVLT | Active | LQFP 208 | ARM Cortex-A5, ARM Cortex-M0+ IOP, ARM Cortex-M4 | 320 | 32/32 on A5 | 1300 | 2000 | 3 | 2 | 5 | 3 | Yes | 2x 16ch | 2x Dual DDR QuadSPI, 16-Bit SDR DRAM (160mhz), 32-Bit DDR2 DRAM (320mhz) | OpenVG 1.1, Segment LCD, 2x 2D-ACE, HUD Warping Engine, Video Input Unit | 8ch PIT, 3x SWT, ARTC, 4x 8ch Flextimer |
封装说明 | Outline Version | 包装 | 产品状态 | 部件编号 | 化学成分 | RoHS / Pb Free中国RoHS查询 | MSL | PPT (°C) |
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MAPBGA 516 27SQ*2.0 P1.0 | 98ASA00623D | MPQ - 200 BRICKPOQ - 400 BOX | Active | SAC57D54HCVMO | SAC57D54HCVMO.pdf | 3 | 260 | |
MPQ - 200 BRICKPOQ - 400 BOX | Active | SAC57D53MCVMO | SAC57D53MCVMO.pdf | 3 | 260 | |||
LQFPEP 208 28SQ P0.5 | 98ASA00649D | MPQ - 180 BRICKPOQ - 360 BOX | Active | SAC57D54HCVLT | SAC57D54HCVLT.pdf | 3 | 260 | |
MPQ - 180 BRICKPOQ - 360 BOX | Active | SAC57D53MCVLT | SAC57D53MCVLT.pdf | 3 | 260 | |||
MPQ - 180 BRICKPOQ - 360 BOX | Active | SAC57D52LCVLT | SAC57D52LCVLT.pdf | 3 | 260 |