MC100EPT25: Translator, Differential LVECL / ECL to LVTTL _ BDTIC 中国领先电子元器件代理商

MC100EPT25: Translator, Differential LVECL / ECL to LVTTL

The MC100EPT25 is a Differential LVECL/ECL to LVTTL translator. This device requires +3.3V, -3.3V to -5.2V, and ground. The small outline 8-lead SOIC package and the single gate of the EPT25 make it ideal for applications which require the translation of a clock or data signal.The VBB output allows the EPT25 to also be used in a single-ended input mode. In this mode the VBB output is tied to the D input for a inverting buffer or the Dbar input for a non-inverting buffer. If used, the VBB pin should be bypassed to ground with at least a 0.01 µF capacitor.

特性

1.1ns Typical Propagation Delay
Maximum Frequency > 275 MHz Typical
Operating Range: VCC = 3.0 V to 3.6 V; VEE = -5.5 V to -3.0 V; GND = 0 V
24mA TTL outputs
Q Output will default LOW with inputs open or at GND
VBB Output
Open Input Default State
Safety Clamp on Inputs
Pb-Free Packages are Available

封装

应用注释 (14)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Clock Management Design Using Low Skew and Low Jitter Devices	TND301/D (205.0kB)	0
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
-3.3 V / -5 V Differential ECL to +3.3 V LVTTL Translator	MC100EPT25/D (160kB)	17	Aug, 2016

仿真模型 (3)

Document Title	Document ID/Size	Revision
EPT21/23/25 ECLinPS PlusE Translator TTL output SPICE Modeling Kit	AND8118/D (53.0kB)	0
IBIS Model for MC100EPT25D VEE -3.3V	MC100EPT25D_-33.IBS (6.0kB)	3
IBIS Model for MC100EPT25D VEE@-5.2V	MC100EPT25D_-52.IBS (6.0kB)	4

封装图纸 (3)

Document Title	Document ID/Size	Revision
DFN8 2.0x2.0x0.9mm, 0.5p	506AA (31.8kB)	F
SOIC-8 Narrow Body	751-07 (62.6kB)	AK
TSSOP 8 3.0x3.0x0.95 mm	948R-02 (77.3kB)	A

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC100EPT25DG	Active	Pb-free Halide free	SOIC-8	751-07	1	Tube	98	联系BDTIC
MC100EPT25DR2G	Active	Pb-free Halide free	SOIC-8	751-07	1	Tape and Reel	2500	联系BDTIC
MC100EPT25DTG	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tube	100	联系BDTIC
MC100EPT25DTR2G	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tape and Reel	2500	联系BDTIC
MC100EPT25MNR4G	Active	Pb-free Halide free	DFN-8	506AA	1	Tape and Reel	1000	联系BDTIC

订购产品技术参数

Product	Channels	Input Level	Output Level	VCC Typ (V)	fMax Typ (MHz)	tpd Typ (ns)	tR & tF Max (ps)
MC100EPT25DG	1	ECL	TTL	3.3	275	0.95	1400 600
MC100EPT25DR2G	1	ECL	TTL	3.3	275	0.95	600 1400
MC100EPT25DTG	1	ECL	TTL	3.3	275	0.95	1400 600
MC100EPT25DTR2G	1	ECL	TTL	3.3	275	0.95	600 1400
MC100EPT25MNR4G	1	ECL	TTL	3.3	275	0.95	1400 600