MC100EPT25: Translator, Differential LVECL / ECL to LVTTL

The MC100EPT25 is a Differential LVECL/ECL to LVTTL translator. This device requires +3.3V, -3.3V to -5.2V, and ground. The small outline 8-lead SOIC package and the single gate of the EPT25 make it ideal for applications which require the translation of a clock or data signal.The VBB output allows the EPT25 to also be used in a single-ended input mode. In this mode the VBB output is tied to the D input for a inverting buffer or the Dbar input for a non-inverting buffer. If used, the VBB pin should be bypassed to ground with at least a 0.01 µF capacitor.

Features
  • 1.1ns Typical Propagation Delay
  • Maximum Frequency > 275 MHz Typical
  • Operating Range: VCC = 3.0 V to 3.6 V; VEE = -5.5 V to -3.0 V; GND = 0 V
  • 24mA TTL outputs
  • Q Output will default LOW with inputs open or at GND
  • VBB Output
  • Open Input Default State
  • Safety Clamp on Inputs
  • Pb-Free Packages are Available
Application Notes (14)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
-3.3 V / -5 V Differential ECL to +3.3 V LVTTL TranslatorMC100EPT25/D (160kB)17Aug, 2016
Simulation Models (3)
Document TitleDocument ID/SizeRevisionRevision Date
EPT21/23/25 ECLinPS PlusE Translator TTL output SPICE Modeling KitAND8118/D (53.0kB)0
IBIS Model for MC100EPT25D VEE -3.3VMC100EPT25D_-33.IBS (6.0kB)3
IBIS Model for MC100EPT25D VEE@-5.2VMC100EPT25D_-52.IBS (6.0kB)4
Package Drawings (3)
Document TitleDocument ID/SizeRevision
DFN8 2.0x2.0x0.9mm, 0.5p506AA (31.8kB)F
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100EPT25DGActivePb-free Halide freeSOIC-8751-071Tube98Contact BDTIC
MC100EPT25DR2GActivePb-free Halide freeSOIC-8751-071Tape and Reel2500Contact BDTIC
MC100EPT25DTGActivePb-free Halide freeTSSOP-8948R-023Tube100Contact BDTIC
MC100EPT25DTR2GActivePb-free Halide freeTSSOP-8948R-023Tape and Reel2500Contact BDTIC
MC100EPT25MNR4GActivePb-free Halide freeDFN-8506AA1Tape and Reel1000Contact BDTIC
Specifications
ProductChannelsInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
MC100EPT25DG1ECLTTL3.32750.951400 600
MC100EPT25DR2G1ECLTTL3.32750.95600 1400
MC100EPT25DTG1ECLTTL3.32750.951400 600
MC100EPT25DTR2G1ECLTTL3.32750.95600 1400
MC100EPT25MNR4G1ECLTTL3.32750.951400 600
-3.3 V / -5 V Differential ECL to +3.3 V LVTTL Translator (160kB) MC100EPT25
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
EPT21/23/25 ECLinPS PlusE Translator TTL output SPICE Modeling Kit MC100EPT25
IBIS Model for MC100EPT25D VEE -3.3V MC100EPT25
IBIS Model for MC100EPT25D VEE@-5.2V MC100EPT25
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
DFN8 2.0x2.0x0.9mm, 0.5p NUF4220
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