MC100LVELT20: LVTTL/LVCMOS to Differential LVPECL Translator
The MC100LVELT20 is a 3.3 V TTL/CMOS to differential PECL translator. Because PECL (Positive ECL) levels are used, only +3.3 V and ground are required. The small outline SOIC−8 package and the single gate of the MC100LVELT20 makes it ideal for those applications where space, performance, and low power are at apremium.The 100 Series contains temperature compensation.
特性
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应用
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封装
应用注释 (12)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| AC Characteristics of ECL Devices | AND8090/D (896.0kB) | 1 | |
| Clock Management Design Using Low Skew and Low Jitter Devices | TND301/D (205.0kB) | 0 | |
| ECL Clock Distribution Techniques | AN1405/D (54.0kB) | 1 | |
| ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide | AND8002 (71kB) | 12 | |
| Interfacing with ECLinPS | AND8066/D (72kB) | 3 | |
| Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks | AND8001/D (90.0kB) | 0 | |
| Phase Lock Loop General Operations | AND8040/D (64.0kB) | 3 | |
| Storage and Handling of Drypack Surface Mount Device | AND8003/D (49kB) | 2 | Mar, 2016 |
| Termination of ECL Logic Devices | AND8020/D (176.0kB) | 6 | |
| The ECL Translator Guide | AN1672/D (142.0kB) | 12 | |
| Thermal Analysis and Reliability of WIRE BONDED ECL | AND8072/D (119.0kB) | 5 | |
| Using Wire-OR Ties in ECLInPS™ Designs | AN1650/D (1130.0kB) | 3 |
数据表 (1)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| 3.3 V LVTTL/LVCMOS to Differential LVPECL Translator | MC100LVELT20/D (130kB) | 1 | Jul, 2016 |
仿真模型 (1)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| IBIS Model for mc100lvelt20d | MC100LVELT20D.IBS (8.0kB) | 0 |
封装图纸 (1)
| Document Title | Document ID/Size | Revision |
|---|---|---|
| SOIC-8 Narrow Body | 751-07 (62.6kB) | AK |
产品订购型号
| 产品 | 状况 | Compliance | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） | ||
|---|---|---|---|---|---|---|---|---|
| MC100LVELT20DG | Active | Pb-free Halide free | SOIC-8 | 751-07 | 1 | Tube | 98 | 联系BDTIC |
| MC100LVELT20DR2G | Active | Pb-free Halide free | SOIC-8 | 751-07 | 1 | Tape and Reel | 2500 | 联系BDTIC |
订购产品技术参数
| Product | Channels | Input Level | Output Level | VCC Typ (V) | fMax Typ (MHz) | tpd Typ (ns) | tR & tF Max (ps) |
|---|---|---|---|---|---|---|---|
| MC100LVELT20DG | 1 | CMOS TTL | ECL | 3.3 | 1000 | 0.37 | 225 |
| MC100LVELT20DR2G | 1 | CMOS TTL | ECL | 3.3 | 1000 | 0.37 | 225 |
- AC Characteristics of ECL Devices NB100LVEP91
- Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
- ECL Clock Distribution Techniques NB100LVEP91
- ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
- Interfacing with ECLinPS NB100LVEP91
- Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
- Phase Lock Loop General Operations MC10H604
- Storage and Handling of Drypack Surface Mount Device NB3U23C
- Termination of ECL Logic Devices NB100LVEP91
- The ECL Translator Guide NB100LVEP91
- Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
- Using Wire-OR Ties in ECLInPS™ Designs MC10H351
- IBIS Model for mc100lvelt20d MC100LVELT20
- SOIC-8 Narrow Body CM1216
