MC100LVELT20: LVTTL/LVCMOS to Differential LVPECL Translator

The MC100LVELT20 is a 3.3 V TTL/CMOS to differential PECL translator. Because PECL (Positive ECL) levels are used, only +3.3 V and ground are required. The small outline SOIC−8 package and the single gate of the MC100LVELT20 makes it ideal for those applications where space, performance, and low power are at apremium.The 100 Series contains temperature compensation.

Features
  • 390 ps Typical Propagation Delay
  • Maximum Input Clock Frequency > 0.8 GHz Typical
  • Operating Range VCC = 3.0 V to 3.6 Vwith GND = 0 V
  • PNP TTL Input for Minimal Loading
  • Pb-Free Packages are Available
Applications
  • Single ended to differential level translation.
Application Notes (12)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
Data Sheets (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3 V LVTTL/LVCMOS to Differential LVPECL TranslatorMC100LVELT20/D (130kB)1Jul, 2016
Simulation Models (1)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for mc100lvelt20dMC100LVELT20D.IBS (8.0kB)0
Package Drawings (1)
Document TitleDocument ID/SizeRevision
SOIC-8 Narrow Body751-07 (62.6kB)AK
Order Information
ProductStatusCompliancePackageMSL*ContainerBudgetary Price/Unit
MC100LVELT20DGActivePb-free Halide freeSOIC-8751-071Tube98Contact BDTIC
MC100LVELT20DR2GActivePb-free Halide freeSOIC-8751-071Tape and Reel2500Contact BDTIC
Specifications
ProductChannelsInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
MC100LVELT20DG1CMOS TTLECL3.310000.37225
MC100LVELT20DR2G1CMOS TTLECL3.310000.37225
3.3 V LVTTL/LVCMOS to Differential LVPECL Translator (130kB) MC100LVELT20
AC Characteristics of ECL Devices NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for mc100lvelt20d MC100LVELT20
SOIC-8 Narrow Body CM1216
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