MC10EP101: 3.3 V / 5.0 V ECL Quad 4-Input OR/NOR Gate
The MC10/100EP101 is a Quad 4-input OR/NOR gate. The device is functionally equivalent to the E101. With AC performance faster than the E101 device, the EP101 is ideal for applications requiring the fastest AC performance available.The 100 Series contains temperature compensation.
特性
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应用
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封装
应用注释 (11)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| AC Characteristics of ECL Devices | AND8090/D (896.0kB) | 1 | |
| Clock Generation and Clock and Data Marking and Ordering Information Guide | AND8002/D (71kB) | 12 | |
| Designing with PECL (ECL at +5.0 V) | AN1406/D (105.0kB) | 2 | |
| ECL Clock Distribution Techniques | AN1405/D (54.0kB) | 1 | |
| ECLinPS Plus™ Spice Modeling Kit | AND8009/D (343.0kB) | 11 | |
| Interfacing Between LVDS and ECL | AN1568/D (121.0kB) | 11 | |
| Interfacing with ECLinPS | AND8066/D (72kB) | 3 | |
| Metastability and the ECLinPS Family | AN1504/D (103.0kB) | 3 | |
| Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks | AND8001/D (90.0kB) | 0 | |
| Termination of ECL Logic Devices | AND8020/D (176.0kB) | 6 | |
| The ECL Translator Guide | AN1672/D (142.0kB) | 12 |
封装图纸 (1)
| Document Title | Document ID/Size | Revision |
|---|---|---|
| QFN32, 5x5, 0.5P, 3.1x3.1EP | 488AM (57.4kB) | A |
数据表 (1)
| Document Title | Document ID/Size | Revision | Revision Date |
|---|---|---|---|
| 3.3V / 5V ECL Quad 4-Input OR/NOR | MC10EP101/D (154.0kB) | 11 |
产品订购型号
| 产品 | 状况 | Compliance | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） | ||
|---|---|---|---|---|---|---|---|---|
| MC10EP101FAG | Active | Pb-free Halide free | LQFP-32 | 联系BDTIC | 2 | Tray JEDEC | 250 | 联系BDTIC |
| MC10EP101FAR2G | Lifetime | Pb-free Halide free | LQFP-32 | 联系BDTIC | 2 | Tape and Reel | 2000 | |
| MC10EP101MNG | Lifetime | Pb-free Halide free | QFN-32 | 488AM | 1 | Tube | 74 | |
| MC10EP101MNR4G | Lifetime | Pb-free Halide free | QFN-32 | 488AM | 1 | Tape and Reel | 1000 | |
订购产品技术参数
| Product | Type | Channels | Input Level | Output Level | VCC Typ (V) | fToggle Max (MHz) | tpd Typ (ns) | tJitter Typ (ps) | tR & tF Max (ps) |
|---|---|---|---|---|---|---|---|---|---|
| MC10EP101FAG | OR/NOR | 4 | CML ECL | ECL | 3.3 5 | 3000 | 0.3 | 0.2 | 200 |
- AC Characteristics of ECL Devices NB100LVEP91
- Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
- Designing with PECL (ECL at +5.0 V) NB100LVEP91
- ECL Clock Distribution Techniques NB100LVEP91
- ECLinPS Plus™ Spice Modeling Kit MC10EPT20
- Interfacing Between LVDS and ECL NB100ELT23L
- Interfacing with ECLinPS NB100LVEP91
- Metastability and the ECLinPS Family MC10EPT20
- Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
- Termination of ECL Logic Devices NB100LVEP91
- The ECL Translator Guide NB100LVEP91
- QFN32, 5x5, 0.5P, 3.1x3.1EP NCN6804
