NB3L8543S: 2.5 V/3.3 V Differential 2:1 MUX to 4 LVDS Clock Fanout Buffer Outputs with Clock Enable and Clock Select
The NB3L8543S is a high performance, low skew 1−to−4 LVDS
Clock Fanout Buffer.
The NB3L8543S features a multiplexed input which can be driven
by either a differential or single−ended input to allow for the
distribution of a lower speed clock along with the high speed system
clock.
The CLK_SEL pin will select the differential CLK and CLKb inputs
when LOW (or left open and pulled LOW by the internal pull−down
resistor). When CLK_SEL is HIGH, the differential PCLK and PCLKb
inputs are selected.
The common clock enable pin, CLK_EN, is synchronous so that the
outputs will only be enabled/disabled when they are already in the
LOW state. This avoids any chance of generating a runt clock pulse on
the outputs during asynchronous assertion/deassertion of the clock
enable pin. The internal flip flop is clocked on the falling edge of the
input clock; therefore, all associated specification limits are
referenced to the negative edge of the clock input.
特性- Four Differential LVDS Output Pairs
- Two Selectable Differential Clock Inputs
- CLK/CLKb Can Accept LVPECL, LVDS, HCSL, HSTL and SSTL
- PCLK/PCLK Can Accept LVPECL, LVDS, CML and SSTL
- Maximum Output Frequency: 650 MHz
- Additive Phase Jitter, RMS: 50 fs (typical)
- Output Skew: 40 ps (maximum)
- Part−to−part Skew: 200 ps (maximum)
- Propagation Delay: 1.9 ns (maximum)
|
应用- Computing
- Telecom
- Backplanes
| 终端产品 |
应用注释 (5)
封装图纸 (1)
| Document Title | Document ID/Size | Revision |
|---|
| TSSOP-20 WB | 948E-02 (39.7kB) | D |
数据表 (1)
产品订购型号
| 产品 | 状况 | Compliance | 封装 | MSL* | 容器 | 预算价格 (1千个数量的单价） |
|---|
| NB3L8543SDTG | Active | Pb-free
Halide free | TSSOP-20 | 948E-02 | 1 | Tube | 75 | 联系BDTIC |
| NB3L8543SDTR2G | Active | Pb-free
Halide free | TSSOP-20 | 948E-02 | 1 | Tape and Reel | 2500 | 联系BDTIC |
订购产品技术参数
| Product | Type | Channels | Input / Output Ratio | Input Level | Output Level | VCC Typ (V) | tJitterRMS Typ (ps) | tskew(o-o) Max (ps) | tpd Typ (ns) | tR & tF Max (ps) | fmaxClock Typ (MHz) | fmaxData Typ (Mbps) |
|---|
| NB3L8543SDTG | Buffer | 1 | 2:1:4 | HCSL
HSTL
CML
LVPECL
SSTL
LVDS | LVDS | 3.3
2.5 | 0.05 | 40 | 1.4 | 550
500 | 650
500 | |
| NB3L8543SDTR2G | Buffer | 1 | 2:1:4 | LVPECL
CML
HSTL
LVDS
SSTL
HCSL | LVDS | 3.3
2.5 | 0.05 | 40 | 1.4 | 550
500 | 650
500 | |
