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NB3L8543S: 2.5 V/3.3 V Differential 2:1 MUX to 4 LVDS Clock Fanout Buffer Outputs with Clock Enable and Clock Select

The NB3L8543S is a high performance, low skew 1−to−4 LVDS Clock Fanout Buffer. The NB3L8543S features a multiplexed input which can be driven by either a differential or single−ended input to allow for the distribution of a lower speed clock along with the high speed system clock. The CLK_SEL pin will select the differential CLK and CLKb inputs when LOW (or left open and pulled LOW by the internal pull−down resistor). When CLK_SEL is HIGH, the differential PCLK and PCLKb inputs are selected. The common clock enable pin, CLK_EN, is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse on the outputs during asynchronous assertion/deassertion of the clock enable pin. The internal flip flop is clocked on the falling edge of the input clock; therefore, all associated specification limits are referenced to the negative edge of the clock input.

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