NB3V8312C: 1-TO-12 LVCMOS/LVTTL _ BDTIC 中国领先电子元器件代理商

NB3V8312C: 1-TO-12 LVCMOS/LVTTL

The NB3V8312C is a high performance, low skew LVCMOS fanout buffer which can distribute 12 ultra-low jitter clocks from an LVCMOS/LVTTL input up to 250 MHz. The 12 LVCMOS output pins drive 50Ωseries or parallel terminated transmission lines. The outputs can also be disabled to a high impedance (tri-stated) via the OE input, or enabled when High. The NB3V8312C provides an enable input, CLK_EN pin, which synchronously enables or disables the clock outputs while in the LOW state. Since this input is internally synchronized to the input clock, changing only when the input is LOW, potential output glitching or runt pulse generation is eliminated. Separate VDD core and VDDO output supplies allow the output buffers to operate at the same supply as the VDD (VDD = VDDO) or from a lower supply voltage. Compared to single-supply operation, dual supply operation enables lower power consumption and output-level compatibility. The VDD core supply voltage can be set to 3.3 V, 2.5 V or 1.8 V, while the VDDO output supply voltage can be set to 3.3 V, 2.5 V, or 1.8 V, with the constraint that VDD >/= VDDO.

特性

VDD core supply voltage can be set to 3.3 V, 2.5 V or 1.8 V
VDDO output supply voltage can be set to 3.3 V, 2.5 V, or 1.8 V, with the constraint that VDD >/= VDDO
250 MHz Maximum Clock Frequency
Accepts LVCMOS, LVTTL Clock Inputs
12 LVCMOS Clock Outputs
150 ps Max. Skew Between Outputs
Temp. Range 40C to +85C
32pin LQFP and QFN Packages
Synchronous Clock Enable

应用

Networking
Telecom
Storage Area Networks

终端产品

Servers
Routers
Switches

应用注释 (6)

Document Title	Document ID/Size	Revision	Revision Date
Board Level Application Notes for DFN and QFN Packages	AND8211/D (175.0kB)	1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)	AND8086/D (40.0kB)	0
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Phase Noise and Additive Phase Jitter Analysis Using the NB3V8312C	AND9151/D (542kB)	1
Semiconductor Package Thermal Characterization	AND8215/D (363.0kB)	0
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
Ultra-Low Jitter, Low Skew 1:12 LVCMOS/LVTTL Fanout Buffer	NB3V8312C/D (153kB)	1

仿真模型 (1)

Document Title	Document ID/Size	Revision	Revision Date
NB3V8312C IBIS Model	NB3V8312C.IBS (85kB)	0	Sep, 2013

封装图纸 (1)

Document Title	Document ID/Size	Revision
QFN32, 5x5, 0.5P, 3.1x3.1EP	488AM (57.4kB)	A

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
NB3V8312CFAG	Active	Pb-free Halide free	LQFP-32	联系BDTIC	2	Tray JEDEC	250	联系BDTIC
NB3V8312CFAR2G	Active	Pb-free Halide free	LQFP-32	联系BDTIC	2	Tape and Reel	2000	联系BDTIC
NB3V8312CMNG	Active	Pb-free Halide free	QFN-32	488AM	1	Tube	74	联系BDTIC
NB3V8312CMNR4G	Active	Pb-free Halide free	QFN-32	488AM	1	Tape and Reel	1000	联系BDTIC

订购产品技术参数

Product	Type	Channels	Input / Output Ratio	Input Level	Output Level	VCC Typ (V)	tJitterRMS Typ (ps)	tskew(o-o) Max (ps)	tpd Typ (ns)	tR & tF Max (ps)	fmaxClock Typ (MHz)
NB3V8312CFAG	Buffer	1	1:12	LVTTL LVCMOS	LVCMOS	1.8 2.5 3.3	0.03	150	1.5	700	250
NB3V8312CFAR2G	Buffer	1	1:12	LVCMOS LVTTL	LVCMOS	3.3 2.5 1.8	0.03	150	1.5	700	250
NB3V8312CMNG	Buffer	1	1:12	LVCMOS LVTTL	LVCMOS	3.3 2.5 1.8	0.03	150	1.5	700	250
NB3V8312CMNR4G	Buffer	1	1:12	LVTTL LVCMOS	LVCMOS	2.5 1.8 3.3	0.03	150	1.5	700	250