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ST33J2M0：32bit ARM SC300 secure core with secure integrity architecture, AES, DES, Nescrypt public key co-processors

The ST33Jxxx (see Table 1) is a serial access microcontroller designed for secure mobile applications. It incorporates the most recent generation of ARM processors for embedded secure systems. Its SecurCore^®SC300™ 32-bit RISC core is built on the Cortex^®-M3 core with additional security features to help to protect against advanced forms of attacks.

The ST33Jxxx provides high performance thanks to a fast SC300 processor, crypto-accelerators and improved Flash memory operations.

Cadenced at 70 MHz, the SC300™ core brings great performance and excellent code density thanks to the Thumb^®-2 instruction set.

Strong and multiple fault protection mechanisms ensure a guaranteed high-detection coverage that facilitates the development of highly secure software. This is achieved by using two CPUs in locked-step mode, error codes in sensitive memories and hardware logic.

The ST33Jxxx offers a serial communication interface fully compatible with the ISO/IEC 7816-3 standard (T=0, T=1) and a single-wire protocol (SWP) interface for communication with a near field communication (NFC) router in Secure Element (SE) applications. The device also includes an SPI Master/Slave interface as well as two I2C Master/Slave interfaces for communication in non-SIM applications: SPI Slave up to 26 MHz, SPI Master up to 13 MHz, I2C Slave High-speed mode up to 3.4 Mbit/s, I2C Master Fast-mode plus up to 1 Mbit/s. Up to four of these interfaces can run independently.

Three general-purpose 16-bit timers as well as a watchdog timer are available.

One permanent timer (PMT) with a count capability up to 8 days in low-power mode is available.

The ST33Jxxx features hardware accelerators for advanced cryptographic functions. The EDES peripheral provides a secure DES (Data Encryption Standard) algorithm implementation, while the NESCRYPT crypto-processor efficiently supports the public key algorithm. The AES peripheral ensures secure and fast AES algorithm implementation.

The ST33Jxxx operates in the –25 to +85 °C temperature range and 1.8 V, 3 V and 5 V supply voltage ranges. A comprehensive range of power-saving modes enables the design of efficient low-power applications:

Key Features

• Hardware features
  • D18 micromodule
  • ECOPACK®-compliant WLCSP12, QFN20 and DFN8 packages
  • Sawn/unsawn 12” wafers
  • External interfaces
    • ISO/IEC 7816-3 T=0 and T=1 protocols (Slave and Master modes)
    • Single Wire Protocol (SWP) slave interface (ETSI 102-613 compliant)
    • Master/slave serial peripheral interface (SPI)
    • Two Master/Slave I2C interfaces
  • Three 16-bit timers with interrupt capability
  • Watchdog timer
  • Eight multiplexed general-purpose I/Os
  • 1.8 V, 3 V and 5 V supply voltage ranges
  • External clock frequency from 1 up to 15 MHz
  • Current consumption compatible with GSM and ETSI specifications
  • Power-saving standby and hibernate states
  • Contact assignment compatible with ISO/IEC 7816-2
  • ESD protection greater than 4 kV (HBM)
  • Delivery forms:
    • D18 micromodule
    • ECOPACK®-compliant WLCSP12, QFN20 and DFN8 packages
    • Sawn/unsawn 12” wafers
    • External interfaces
      • ISO/IEC 7816-3 T=0 and T=1 protocols (Slave and Master modes)
      • Single Wire Protocol (SWP) slave interface (ETSI 102-613 compliant)
      • Master/slave serial peripheral interface (SPI)
      • Two Master/Slave I2C interfaces
    • Three 16-bit timers with interrupt capability
    • Watchdog timer
    • Eight multiplexed general-purpose I/Os
    • 1.8 V, 3 V and 5 V supply voltage ranges
    • External clock frequency from 1 up to 15 MHz
    • Current consumption compatible with GSM and ETSI specifications
    • Power-saving standby and hibernate states
    • Contact assignment compatible with ISO/IEC 7816-2
    • ESD protection greater than 4 kV (HBM)
• Security features
  • Platform and Flash loader security certification target according to CC EAL6+ / EMVCo
  • Hardware security-enhanced DES accelerator
  • Hardware security-enhanced AES accelerator
  • MIFARE® Classic cryptography hardware accelerator
  • NESCRYPT coprocessor for public key cryptography algorithm
  • 16- and 32-bit CRC calculation block (ISO 13239, IEEE 802.3, etc.)
  • Active shield
  • Memory management unit
  • Highly efficient protection against faults
  • True random number generator
  • Permanent timer
• Software features
  • Secure Flash loader with high-speed downloading and post-delivery loading ability
  • Optional NesLib public cryptographic library
  • Optional MIFARE4Mobile® v2.1.1 with MIFARE® Classic, DESFire® EV1

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