74AUP1G126：Single Gate
| Part Number | Data Sheet | SPICE Model | Number of Gates | Family | VCC Min (V) | VCC Max (V) | tpd max @ (1.5V) (ns) | tpd max @ (1.8V) (ns) | tpd max @ (2.5V) (ns) | tpd max @ (3.3V) (ns) | tpd max @ (5.0V) (ns) | Output Current |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AUP1G126 | 74AUP1G126.pdf | - | 1 | AUP | 0.8 | 3.6 | 8.1 | 6.3 | 4.9 | 4.4 | - | 4 |
Description
The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended battery life in portable applications. The 74AUP1G126 is a single non-inverting buffer/bus driver designed for operation over a power supply range of 0.8V to 3.6V. The device has a 3-state output that enters a high impedance state when a LOW-level is applied to the output enable (OE) pin. The device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output preventing damaging current backflow when the device is powered down.
Application
- Suited for battery and low power needs
- Wide array of products such as:
Features
- Advanced Ultra Low Power (AUP) CMOS
- Supply Voltage Range from 0.8V to 3.6V
- ±4mA Output Drive at 3.0V
- Low Static power consumption
Ordering Information
- 74AUP1G126FS3-7
- 74AUP1G126FW4-7
- 74AUP1G126FW5-7
- 74AUP1G126FZ4-7
- 74AUP1G126SE-7
SOT353
X2-DFN1010-6
X2-DFN1410-6
- 74AUP1G126.pdf 74AUP1G126
- 74LVC2G34 dual buffer 74LVC2G34
- 74LVC2G34 dual buffer 74LVC2G34
