74LVC373A：Standard Logic _ BDTIC a Leading Distributor in China

74LVC373A：Standard Logic

Part Number	Data Sheet	SPICE Model	Number of Gates	Family	VCC Min (V)	VCC Max (V)	tpd max @ (1.5V) (ns)	tpd max @ (1.8V) (ns)	tpd max @ (2.5V) (ns)	tpd max @ (3.3V) (ns)	tpd max @ (5.0V) (ns)	Input/ Output Current
74LVC373A	74LVC373A.pdf	-	8	LVC	1.65	3.6	-	14.8	10	7.2	-	24

Description

The 74LVC373A provides eight transparent D-type latches. While the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the logic levels set up at the D inputs. A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the highimpedance state.

The device is designed for operation with a power supply range of 1.65V to 3.6V.

The inputs are tolerant to 5.5V allowing this device to be used in a mixed voltage environment. The device is fully specified for partial power down applications using I_OFF. The I_OFF circuitry disables the output preventing damaging current backflow when the device is powered down.

Application

General Purpose Logic
Bus Driving
Power Down Signal Isolation
Wide Array of Products Such as:
- PCs, Notebooks, Netbooks, Ultrabooks
- Networking Computer Peripherals, Hard Drives, CD/DVD ROM
- TV, DVD, DVR, Set Top Box

Features

Supply Voltage Range from 1.65V to 3.6V
Sinks or Sources 24mA at V_CC = 3V
CMOS Low Power Consumption
I_OFF Supports Partial -Power Down Operation
Inputs or Outputs Accept up to 5.5V
Inputs Can Be Driven by 3.3V or 5V Allowing for Mixed Voltage Applications
Schmitt Trigger Action at All Inputs
Typical V_OLP (Quiet Output Ground Bounce) Less than 0.8V with V_CC = 3.3V and T_A = +25°C
Typical V_OHV (Quiet Output dynamic VOH) Greater than 2.0V with V_CC = 3.3V and T_A = +25°C
ESD Protection Tested per JESD 22
- Exceeds 200-V Machine Model (A115)
- Exceeds 2000-V Human Body Model (A114)
- Exceeds 1000-V Charged Device Model (C101)
Latch-Up Exceeds 250mA per JESD 78, Class I
All devices are:
- Totally Lead-Free & Fully RoHS compliant
- Halogen and Antimony Free.“Green” Device