Features

• Firmware Hub for Intel 8xx Chipsets
• 8 Mbit SuperFlash memory array for code/datastorage– 1024K x8
• Flexible Erase Capability– Uniform 4 KByte Sectors– Uniform 64 KByte overlay blocks– 64 KByte Top Boot Block protection– Chip-Erase for PP Mode Only
• Single 3.0-3.6V Read and Write Operations
• Superior Reliability– Endurance:100,000 Cycles (typical)– Greater than 100 years Data Retention
• Low Power Consumption– Active Read Current: 6 mA (typical)– Standby Current: 10 µA (typical)
• Fast Sector-Erase/Byte-Program Operation Sector-Erase Time: 18 ms (typical)  Block-Erase Time: 18 ms (typical) Chip-Erase Time: 70 ms (typical) Byte-Program Time: 14 µs (typical) Chip Rewrite Time: 15 seconds (typical) Single-pulse Program or Erase– Internal timing generation
• Sector-Erase Time: 18 ms (typical)
• Block-Erase Time: 18 ms (typical)
• Chip-Erase Time: 70 ms (typical)
• Byte-Program Time: 14 µs (typical)
• Chip Rewrite Time: 15 seconds (typical)
• Single-pulse Program or Erase– Internal timing generation
• Two Operational Modes– Firmware Hub Interface (FWH) Mode forIn-System operation– Parallel Programming (PP) Mode for fastproduction programming
• Firmware Hub Hardware Interface Mode– 5-signal communication interface supportingbyte Read and Write– 33 MHz clock frequency operation– WP# and TBL# pins provide hardware writeprotect for entire chip and/or top Boot Block– Block Locking Register for all blocks– Standard SDP Command Set– Data# Polling and Toggle Bit for End-of-Writedetection– 5 GPI pins for system design flexibility– 4 ID pins for multi-chip selection
• Parallel Programming (PP) Mode– 11-pin multiplexed address and8-pin data I/O interface– Supports fast In-System or PROM programmingfor manufacturing
• CMOS and PCI I/O Compatibility
• Packages Available– 32-lead PLCC– 32-lead TSOP (8mm x 14mm)– 40-lead TSOP (10mm x 20mm)– Non-Pb (lead-free) packages available
• All non-Pb (lead-free) devices are RoHS compliant

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