74ALVCH16501DL: 18-bit universal bus transceiver; 3-state

The 74ALVCH16501 is an 18-bit transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OEBA), latch enable (LEAB and LEBA), and clock (CPAB and CPBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is HIGH. When LEAB is LOW, the A data is latched if CPAB is held at a HIGH or LOW logic level. If LEAB is LOW, the A-bus data is stored in the latch/flip-flop on the LOW-to HIGH transition of CPAB. When OEAB is HIGH, the outputs are active. When OEAB is LOW, the outputs are in the high-impedance state.

Data flow for B-to-A is similar to that of A-to-B but uses OEBA, LEBA and CPBA. The output enables are complimentary (OEAB is active HIGH, and OEBA is active LOW).

To ensure the high-impedance state during power-up or power-down, OEBA should be tied to VCC through a pull-up resistor and OEAB should be tied to GND through a pull-down resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.

Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.

74ALVCH16501DL: Product Block Diagram

Outline 3d SOT371-1

Data Sheets (1)

Name/Description	Modified Date
18-bit universal bus transceiver; 3-state (REV 5.0) PDF (225.0 kB) 74ALVCH16501 [English]	10 Jul 2012

Application Notes (4)

Name/Description	Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]	13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]	13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]	13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]	13 Mar 2013

Brochures (3)

Name/Description	Modified Date
Low voltage CMOS family - LVC (REV 1.0) PDF (2.6 MB) 75017668 [English]	10 Jul 2015
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]	16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]	20 May 2014

Selector Guides (2)

Name/Description	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]	08 Jan 2015

Package Information (1)

Name/Description	Modified Date
plastic shrink small outline package; 56 leads; body width 7.5 mm (REV 1.0) PDF (530.0 kB) SOT371-1 [English]	08 Feb 2016

Supporting Information (2)

Name/Description	Modified Date
Footprint for reflow soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-REFLOW [English]	08 Oct 2009
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]	08 Oct 2009

IBIS Model

alvch16501 IBIS model (REV 1.0) ibs ALVCH16501 4/7/2013

Ordering Information

Product	Status	Family	Function	V_CC (V)	Description	Logic switching levels	Output drive capability	Package version	t_pd (ns)	No of bits	f_max (MHz)	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74ALVCH16501DL	Active	ALVC	Transceivers	1.65 - 3.6	positive edge trigger (3-state)	TTL	+/- 24	SOT371-1	2.8	18	150	low		84	24.0		SSOP56	56

Package Information

Product ID	Package Description	Outline Version	Reflow/Wave Soldering	Packing	Product Status	Part NumberOrdering code(12NC)	Marking	Chemical Content	RoHS / Pb Free / RHF	LeadFree Conversion Date	EFR	IFR(FIT)	MTBF(hour)	MSL	MSL LF
74ALVCH16501DL		SOT371-1	SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE	Reel 13" Q1/T1	Active	74ALVCH16501DL,118 (9352 638 82118)	ALVCH16501	74ALVCH16501DL		week 15, 2005	123.8	3.87	2.58E8	1	2
74ALVCH16501DL		SOT371-1		Bulk Pack	Active	74ALVCH16501DL,112 (9352 638 82112)	ALVCH16501	74ALVCH16501DL		week 15, 2005	123.8	3.87	2.58E8	1	2