74ALVT16821DGG: 20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state
The 74ALVT16821 high-performance Bipolar Complementary Metal Oxide Semiconductor (BiCMOS) device combines low static and dynamic power dissipation with high speed and high output drive. It is designed for VCC operation at 2.5 V or 3.3 V with I/O compatibility to 5 V.
The 74ALVT16821 has two 10-bit, edge triggered registers, with each register coupled to a 3-state output buffer. The two sections of each register are controlled independently by the clock (nCP) and output enable (nOE) control gates.
Each register is fully edge triggered. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flops Q output.
The 3-state output buffers are designed to drive heavily loaded 3-state buses, MOS memories, or MOS microprocessors.
The active low output enable (nOE) controls all ten 3-state buffers independent of the register operation. When nOE is LOW, the data in the register appears at the outputs. When nOE is HIGH, the outputs are in high-impedance OFF-state, which means they will neither drive nor load the bus.
74ALVT16821DGG: Product Block Diagram
74ALVT16821DGG: Block Diagram
74ALVT16821DGG: Block Diagram
Outline 3d SOT364-1
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| 20-bit bus interface D-type flip-flop; positive-edge trigger; 3-state (REV 3.0) PDF (106.0 kB) 74ALVT16821 [English] | 13 Jun 2005 |
Application Notes (8)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English] | 13 Mar 2013 |
| Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English] | 13 Mar 2013 |
| Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English] | 13 Mar 2013 |
| Test Fixtures for High Speed Logic (REV 1.0) PDF (341.0 kB) AN203 [English] | 02 Apr 1998 |
| Transmission Lines and Terminations with Philips Advanced Logic Families (REV 1.0) PDF (217.0 kB) AN246 [English] | 01 Feb 1998 |
| LVT (Low Voltage Technology) and ALVT (Advanced LVT) (REV 1.0) PDF (133.0 kB) AN243 [English] | 01 Jan 1998 |
| Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English] | 15 Sep 1995 |
Brochures (2)
| Name/Description | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Selector Guides (2)
| Name/Description | Modified Date |
|---|---|
| ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
| Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| plastic thin shrink small outline package; 56 leads; body width 6.1 mm (REV 1.0) PDF (506.0 kB) SOT364-1 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| TSSOP56; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 4.0) PDF (248.0 kB) SOT364-1_118 [English] | 15 Apr 2013 |
Supporting Information (1)
| Name/Description | Modified Date |
|---|---|
| Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English] | 08 Oct 2009 |
IBIS Model
- alvt16821 IBIS model (REV 1.0) ibs ALVT16821 4/7/2013
SPICE model
- alvt16 Spice model (REV 1.0) ZIP ALVT16 5/7/2013
Ordering Information
| Product | Status | Family | Function | VCC (V) | Logic switching levels | Description | Output drive capability (mA) | Package version | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74ALVT16821DGG | Active | ALVT | D-type flip-flops | 2.3 - 3.6 | TTL | positive-edge trigger (3-state) | -32/+64 | SOT364-1 | 1.8 | 150 | medium | -40~85 | 93 | 21.0 | TSSOP56 | 56 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74ALVT16821DGG | | SOT364-1 | SSOP-TSSOP-VSO-WAVE | Tube in Drypack | Active | 74ALVT16821DGGS (9352 100 10512) | ALVT16821 | 74ALVT16821DGG |    | Always Pb-free | 70.8 | 1.33 | 7.52E8 | 2 | 2 |
| Reel 13" Q1/T1 in Drypack | Active | 74ALVT16821DGGY (9352 100 10518) | ALVT16821 | 74ALVT16821DGG | | Always Pb-free | 70.8 | 1.33 | 7.52E8 | 2 | 2 |
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
- Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100
- Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100
- Test Fixtures for High Speed Logic 74ABTH162245ADL
- Transmission Lines and Terminations with Philips Advanced Logic Families 74LVTN16245BDGG
- LVT (Low Voltage Technology) and ALVT (Advanced LVT) 74LVTN16245BDGG
- Interfacing 3 Volt and 5 Volt Applications 74LVC377PW
- 電圧レベルシフタ 74AVC16245DGG-Q100
- Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
- ロジック製品セレクションガイド... 74LVC_H_245A_Q100
- Logic selection guide 2016 74LVC_H_245A_Q100
- TSSOP56; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... pcf8576d_automotive
- alvt16821 IBIS model 74ALVT16821DL
- alvt16 Spice model 74ALVT16827DL
- plastic thin shrink small outline package; 56 leads; body width 6.1 mm pcf8576d_automotive
- SSOP-TSSOP-VSO-WAVE LPC1114FDH28
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