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ST33G640SM：32bit ARM SC300 secure core with MIFARE™ , SWP for Secure Element and SIM-SWP

The ST33GxxxSM is a serial access microcontroller designed for secure mobile applications that incorporates the most recent generation of ARM® processors for embedded secure systems. Its SecurCore® SC300™ 32-bit RISC core is built on the Cortex® M3 core with additional security features to help to protect against advanced forms of attacks.

The SC300™ core brings great performance and excellent code density thanks to the Thumb®-2 instruction set.

The high-speed embedded Flash memory introduces more flexibility to the system.

The ST33GxxxSM also offers a serial communication interface fully compatible with the ISO/IEC 7816-3 standard (T=0, T=1) and a single-wire protocol (SWP) interface for communication with a near field communication (NFC) router in SIM/NFC applications.

The ST33GxxxSM embeds a MIFARE® Library fully compatible with the widely deployed MIFARE® Classic and MIFARE DESFire® EV1 contactless scheme. Both MIFARE® Classic and MIFARE DESFire® EV1 can be used in mobile contactless applications such as Transport & Event ticketing, Access Control, Loyalty programs.

An SPI Master/Slave interface is also available for communication in non-SIM applications.

The ST33GxxxSM features hardware accelerators for advanced cryptographic functions. The EDES peripheral provides a secure DES (Data Encryption Standard) algorithm implementation, while the NESCRYPT crypto-processor efficiently supports the public key algorithm. The AES peripheral ensures secure and fast AES algorithm implementation.

The ST33GxxxSM operates in the –25 to +85 °C temperature range and 1.8 V, 3 V and 5 V supply voltage ranges. A comprehensive range of power-saving modes enables the design of efficient low-power applications.

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK^®packages, depending on their level of environmental compliance. ECOPACK^®specifications, grade definitions and product status are available at: www.st.com. ECOPACK^®is an ST trademark.

Key Features

• Hardware features
  • D18 micromodules
  • sawn 12” wafers
  • ECOPACK®-compliant WLCSP8, DFN8 5 × 6 mm and UFDFN8 4.2 × 4 mm packages
  • Asynchronous receiver transmitter supporting ISO/IEC 7816-3 T=0 and T=1 protocols (Slave mode supported)
  • Single wire protocol (SWP) interface for communications with NFC router (ETSI 102-613 compliant)
  • Serial peripheral interface (SPI) master/slave interface
  • Three 16-bit timers with interrupt capability
  • Seven general-purpose I/Os enabling proprietary protocol implementation
  • 1.8 V, 3 V and 5 V supply voltage ranges
  • External clock frequency from 1 up to 10 MHz
  • Current consumption compatible with GSM and ETSI specifications
  • Power-saving standby state
  • Contact assignment compatible with ISO/IEC 7816-2
  • ESD protection greater than 4 kV (HBM)
  • Delivery forms:
    • D18 micromodules
    • sawn 12” wafers
    • ECOPACK®-compliant WLCSP8, DFN8 5 × 6 mm and UFDFN8 4.2 × 4 mm packages
    • Asynchronous receiver transmitter supporting ISO/IEC 7816-3 T=0 and T=1 protocols (Slave mode supported)
    • Single wire protocol (SWP) interface for communications with NFC router (ETSI 102-613 compliant)
    • Serial peripheral interface (SPI) master/slave interface
    • Three 16-bit timers with interrupt capability
    • Seven general-purpose I/Os enabling proprietary protocol implementation
    • 1.8 V, 3 V and 5 V supply voltage ranges
    • External clock frequency from 1 up to 10 MHz
    • Current consumption compatible with GSM and ETSI specifications
    • Power-saving standby state
    • Contact assignment compatible with ISO/IEC 7816-2
    • ESD protection greater than 4 kV (HBM)
• Software features
  • Secure Flash memory loader
  • Flash memory drivers
  • MIFARE® libraries1: MIFARE® Classic, MIFARE DESFire® EV1
• Security features
  • MIFARE® Classic cryptography hardware accelerator
  • Active shield
  • Memory protection unit (MPU)
  • Monitoring of environmental parameters
  • Protection against faults
  • 16- and 32-bit CRC calculation block (ISO 13239, IEEE 802.3, etc.)
  • True random number generator
  • Unique serial number on each die
  • Hardware security-enhanced DES accelerator
  • Hardware security-enhanced AES accelerator
  • NESCRYPT coprocessor for public key cryptography algorithm

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