NB100LVEP17: Quad Differential Driver/Receiver/Buffer _ BDTIC 中国领先电子元器件代理商

NB100LVEP17: Quad Differential Driver/Receiver/Buffer

The NB100LVEP17 is a 4-bit differential line receiver. The design incorporates two stages of gain, internal to the device, making it an excellent choice for use in high bandwidth amplifier applications.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.Inputs of unused gates can be left open and will not affect the operation of the rest of the device.

特性

250 ps Typical Propagation Delay
Maximum Frequency >2.5 GHz Typical
Flow through Pinout
PECL Mode Operating Range: VCC = 2.375 V to 3.8 V, with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V, with VEE = -2.375 V to -3.8 V
Q Output will Default LOW with Inputs Open or at VEE
VBB Output

封装

应用注释 (13)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)	AND8086/D (40.0kB)	0
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS Plus™ Spice Modeling Kit	AND8009/D (343.0kB)	11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5

封装图纸 (2)

Document Title	Document ID/Size	Revision
QFN24, 4x4, 0.5P	485L-01 (60.0kB)	B
TSSOP-20 WB	948E-02 (39.7kB)	D

仿真模型 (4)

Document Title	Document ID/Size	Revision
IBIS Model for NB100LVEP17MN -3.3V	NB100LVEP17MN_-33.IBS (9.0kB)	2
IBIS Model for nb100lvep17dt 2.5V	NB100LVEP17DT_25.IBS (9.0kB)	1
IBIS Model for nb100lvep17dt 3.3V	NB100LVEP17DT_33.IBS (9.0kB)	q
IBIS Model for nb100lvep17mn 3.3V	NB100LVEP17MN_33.IBS (9.0kB)	1

评估板文档 (1)

Document Title	Document ID/Size	Revision	Revision Date
Evaluation Board User's Manual for High Frequency TSSOP 20	EVBUM2057/D (247.0kB)	2

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
2.5V / 3.3V ECL Quad Differential Driver/Receiver	NB100LVEP17/D (99kB)	8

评估板与开发工具

产品	状况	Compliance	简短说明
ECLTSSOP20EVB	Active		High Frequency TSSOP20 Evaluation Board

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
NB100LVEP17DT	Obsolete	Pb-free	TSSOP-20	948E-02	1	Tube	75
NB100LVEP17DTG	Active	Pb-free Halide free	TSSOP-20	948E-02	1	Tube	75	联系BDTIC
NB100LVEP17DTR2	Obsolete	Pb-free	TSSOP-20	948E-02	1	Tape and Reel	2500
NB100LVEP17DTR2G	Active	Pb-free Halide free	TSSOP-20	948E-02	1	Tape and Reel	2500	联系BDTIC
NB100LVEP17MNG	Active	Pb-free Halide free	QFN-24	485L-01	1	Tube	92	联系BDTIC
NB100LVEP17MNR2G	Active	Pb-free Halide free	QFN-24	485L-01	1	Tape and Reel	3000	联系BDTIC

订购产品技术参数

Product	Type	Channels	Input / Output Ratio	Input Level	Output Level	VCC Typ (V)	tJitterRMS Typ (ps)	tskew(o-o) Max (ps)	tpd Typ (ns)	tR & tF Max (ps)	fmaxClock Typ (MHz)	fmaxData Typ (Mbps)
NB100LVEP17DTG	Signal Driver	4	1:1	ECL CML LVDS	ECL	3.3 2.5 5	0.5	25	0.25	225	2500	2500
NB100LVEP17DTR2G	Signal Driver	4	1:1	ECL CML LVDS	ECL	3.3 5 2.5	0.5	25	0.25	225	2500	2500
NB100LVEP17MNG	Signal Driver	4	1:1	CML ECL LVDS	ECL	5 3.3 2.5	0.5	25	0.25	225	2500	2500
NB100LVEP17MNR2G	Signal Driver	4	1:1	CML LVDS ECL	ECL	5 2.5 3.3	0.5	25	0.25	225	2500	2500