NB3N106K: Clock Fanout Buffer, 1:6 Differential, 3.3 V, with HCSL Outputs

The NB3N106K is a differential 1:6 Clock and Data fanout buffer with High-speed Current Steering Logic (HCSL) outputs optimized for ultra low propagation delay variation. The NB3N106K is designed with HCSL clock distribution and FBDIMM applications in mind.

特性

0.1 ps Typical RMS Phase Jitter
Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
Typical Input Clock Frequency 100, 133, 166, 200, 266, 333, and 400 MHz
220 ps Typical Rise and Fall Times
800 ps Typical Propagation Delay
100 ps Maximum tpd Propagation Delay Variation per Diff Pair
Differential HCSL Output Levels

优势

Best in class for jitter performance
Conforms to Industry Standards
Wide range of clock frequencies

应用

Clock Distribution
PCIe I, II, III
Networking and Communications
High End Computing
General High Performance HCSL Fanout buffer
HCSL FBDIMM Memory CLOCK buffer

终端产品

Servers
Ethernet Switchers / Routers
FBDIMM Memory Card

应用注释 (6)

Document Title	Document ID/Size	Revision	Revision Date
A System Designer's Guide for Building a PCIe Clock Tree while Addressing Timing Challenges	AND9202/D (179kB)	1	Mar, 2015
Board Level Application Notes for DFN and QFN Packages	AND8211/D (175.0kB)	1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)	AND8086/D (40.0kB)	0
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Semiconductor Package Thermal Characterization	AND8215/D (363.0kB)	0
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016