NB3N853531E: Xtal Input or LVTTL / LVCMOS Input Mux - 2:1, 3.3 V, Fanout Buffer- 1:4 LVPECL

The NB3N853531E is a low skew 3.3 V supply 2:1:4 clock distribution fanout buffer. An input MUX selects either a Fundamental Parallel Mode Crystal or a LVCMOS/LVTTL Clock by using the CLK_SEL pin (HIGH for Crystal, LOW for Clock) with LVCMOS / LVTTL levels. The single ended CLK input is translated to four LVPECL Outputs. Using the crystal input, the NB3N853531E can be a Clock Generator. A CLK_EN pin can enable or disable the outputs synchronously to eliminate runt pulses using LVCMOS/LVTTL levels (HIGH to enable outputs, LOW to disable output).

特性

Four Differential LVPECL Outputs
Selectable Crystal or LVCMOS/LVTTL CLOCK Inputs
Operating Range: VCC = 3.3 5% V( 3.135 to 3.465 V)
PbFree TSSOP20 Package
Up to 266 MHz Clock Operation
Output to Output Skew: 30 ps (Typ)
Device to Device Skew 200 ps (Max)
Propagation Delay 1.8 ns (Max)
Additive Phase Jitter, RMS: 0.053 ps (Typ.)
Synchronous Clock Enable Control
Industrial Temp. Range (40C to 85C)
These are PbFree Devices
10Gigibit Ethernet

优势

Multiple copies of the Clock
Accepts inexpensive crystals
Ensures operation in the majority of designs
Meets all green international materials standards

应用

Gigibit Ethernet
SONET/SDH
Teleconmmunications

终端产品

LAN/WAN
Enterprise Servers
ATE
Test and Measurement

应用注释 (7)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Board Level Application Notes for DFN and QFN Packages	AND8211/D (175.0kB)	1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)	AND8086/D (40.0kB)	0
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Semiconductor Package Thermal Characterization	AND8215/D (363.0kB)	0
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3 V Xtal Input or LVTTL/LVCMOS 2:1 MUX to 1:4 LVPECL Fanout Buffer	NB3N853531E/D (246.0kB)	6

仿真模型 (1)

Document Title	Document ID/Size	Revision	Revision Date
NB3N853531E IBIS Model	NB3N853531E.ibs (50kB)	0	Jul, 2015

封装图纸 (1)

Document Title	Document ID/Size	Revision
TSSOP-20 WB	948E-02 (39.7kB)	D

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
NB3N853531EDTG	Active	Pb-free Halide free	TSSOP-20	948E-02	1	Tube	75	联系BDTIC
NB3N853531EDTR2G	Active	Pb-free Halide free	TSSOP-20	948E-02	1	Tape and Reel	2500	联系BDTIC