NB4N316M: AnyLevel™ Input to Open Collector CML Output Buffer/ Translator w/ Input Hysteresis

The NB4N316M is a differential Clock or Data receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to CML, operating up to 2.0 GHz or 2.5 Gb/s, respectively. As such, the NB4N316M is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock or Data distribution applications. The CML outputs are 16 mA open collector which require a resistor load path to VTT termination voltage. The open collector CML outputs must be terminated to VTT at power up. The differential outputs produce Current Mode Logic (CML) compatible levels when the receiver is loaded with 50-ohm or 25-ohm loads connected to 1.8 V, 2.5 V or 3.3 V supplies. This simplifies device interface by eliminating a need for coupling capacitors. The NB4N316M features an input threshold of approximately 25mV, providibg increased noise immunity and stability. The device is offered in a small 8-pin TSSOP package (MSOP-8 compatible).

特性

Maximum Input Clock Frequency > 2.0 GHz
Maximum Input Data Rate > 2.5 Gb/s
Typically 1 ps of RMS Clock Jitter
Typically 10 ps of Data Dependent Jitter
550 ps Typical Propagation Delay
150 ps Typical Rise and Fall Times
Differential Open Collector CML Outputs

应用

Signal interface translation for Networking and ATE
High Speed CLOCK Applications

应用注释 (6)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
ECLinPS Plus™ Spice Modeling Kit	AND8009/D (343.0kB)	11
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination and Interface of ON Semiconductor ECL Logic Devices with CML (Current Mode Logic) Output Structure	AND8173/D (144.0kB)	3
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3 V AnyLevel Receiver to CML Driver/Translator with Input Hysteresis - 2.0 GHz Clock / 2.5 Gb/s Data	NB4N316M/D (153kB)	6

仿真模型 (1)

Document Title	Document ID/Size	Revision	Revision Date
IBIS Model for NB4N316M	NB4N316M.IBS (20.0kB)	1

封装图纸 (1)

Document Title	Document ID/Size	Revision
TSSOP 8 3.0x3.0x0.95 mm	948R-02 (77.3kB)	A

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
NB4N316MDTG	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tube	100	联系BDTIC
NB4N316MDTR2G	Active	Pb-free Halide free	TSSOP-8	948R-02	3	Tape and Reel	2500	联系BDTIC

订购产品技术参数

Product	Type	Channels	Input / Output Ratio	Input Level	Output Level	VCC Typ (V)	tJitterRMS Typ (ps)	tskew(o-o) Max (ps)	tpd Typ (ns)	tR & tF Max (ps)	fmaxClock Typ (MHz)	fmaxData Typ (Mbps)
NB4N316MDTG	Signal Driver	1	1:1	LVDS TTL ECL CML HSTL CMOS	CML	3.3	1	20	0.55	300	2000	2500
NB4N316MDTR2G	Signal Driver	1	1:1	TTL CML ECL CMOS HSTL LVDS	CML	3.3	1	20	0.55	300	2000	2500