SN54LS156 双路 2 线路至 4 线路解码器/多路解复用器
These monolithic transistor-transistor-logic (TTL) circuits feature dual 1-line-to-4-line demultiplexers with individual strobes and common binary-address inputs in a single 16-pin package. When both sections are enabled by the strobes, the common binary-address inputs sequentially select and route associated input data to the appropriate output of each section. The individual strobes permit activating or inhibiting each of the 4-bit sections as desired. Data applied to input 1C is inverted at its outputs and data applied at 2C\ is not inverted through its outputs. The inverter following the 1C data input permits use as a 3-to-8-line decoder or 1-to-8-line demultiplexer without external gating. Input clamping diodes are provided on all of these circuits to minimize transmission-line effects and simplify system design.
| SN54LS156 | |
| Rating | Military |
| Technology Family | LS |
SN54LS156 特性
- Applications:
- Dual 2-to 4-Line Decoder
- Dual 1-to 4-Line Demultiplexer
- 3-to 8-Line Decoder
- 1-to 8-Line Demultiplexer
- Individual Strobes Simplify Cascading for Decoding or Demultiplexing Larger Words
- Input Clamping Diodes Simplify System Design
- Choice of Outputs:
- Totem Pole ('155, 'LS155A)
- Open-Collector ('156, 'LS156)
SN54LS156 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SNJ54LS156FK | ACTIVE | -55 to 125 | 11.77 | 1ku | LCCC (FK) | 20 | 1 | TUBE | |
| SNJ54LS156J | ACTIVE | -55 to 125 | 2.49 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
| SNJ54LS156W | ACTIVE | -55 to 125 | 12.36 | 1ku | CFP (W) | 16 | 1 | TUBE |
SN54LS156 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SNJ54LS156FK | TBD | POST-PLATE | N/A for Pkg Type | SNJ54LS156FK | SNJ54LS156FK |
| SNJ54LS156J | TBD | A42 | N/A for Pkg Type | SNJ54LS156J | SNJ54LS156J |
| SNJ54LS156W | TBD | A42 | N/A for Pkg Type | SNJ54LS156W | SNJ54LS156W |
SN54LS156 应用技术支持与电子电路设计开发资源下载
- SN54LS156 数据资料 dataSheet 下载.PDF
- TI 德州仪器MSI 功能产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
