SN54LS193 同步 4 位加/减计数器（具有双路时钟和清零功能）
These monolithic circuits are synchronous reversible (up/down) counters having a complexity of 55 equivalent gates. The '192 and 'LS192 circuits are BCD counters and the '193 and 'LS193 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidently with each other when so instructed by the steering logic. This mode of operation eliminates the output counting spikes which are normally associated with asynchronous (ripple-clock) counters.
The outputs of the four master-slave flip-flops are triggered by a low-to-high-level transition of either count (clock) input. The direction of counting is determined by which count input is pulsed while the other count input is high
| SN54LS193 | |
| Rating | Military |
| Technology Family | LS |
SN54LS193 特性
- Cascading Circuitry Provided Internally
- Synchronous Operation
- Individual Preset to Each Flip-Flop
- Fully Independent Clear Input
SN54LS193 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN54LS193J | ACTIVE | -55 to 125 | 3.78 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
| SNJ54LS193AJ | ACTIVE | -55 to 125 | 4.43 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
| SNJ54LS193AW | ACTIVE | -55 to 125 | 16.24 | 1ku | CFP (W) | 16 | 1 | TUBE |
SN54LS193 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN54LS193J | TBD | A42 | N/A for Pkg Type | SN54LS193J | SN54LS193J |
| SNJ54LS193AJ | TBD | A42 | N/A for Pkg Type | SNJ54LS193AJ | SNJ54LS193AJ |
| SNJ54LS193AW | TBD | A42 | N/A for Pkg Type | SNJ54LS193AW | SNJ54LS193AW |
SN54LS193 应用技术支持与电子电路设计开发资源下载
- SN54LS193 数据资料 dataSheet 下载.PDF
- TI 德州仪器MSI 功能产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
