SN54LVC257A 具有三态输出的四路 2 线路到 1 线路数据选择器/多路复用器
These quadruple 2-line to 1-line data selectors/multiplexers are designed for 1.65-V to 3.6-V VCC operation.
The ’LVC257A devices are designed to multiplex signals from 4-bit data sources to 4-output data lines in bus-organized systems. The 3-state outputs do not load the data lines when the output-enable (OE)\ input is at a high logic level.
Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.
To ensure the high-impedance state during power up or power down, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver
| SN54LVC257A | |
| Rating | Military |
| Technology Family | LVC |
SN54LVC257A 特性
- Operate From 1.65 V to 3.6 V
- Inputs Accept Voltages to 5.5 V
- Max tpd of 4.6 ns at 3.3 V
- Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
- Latch-Up Performance Exceeds 250 mA Per JESD 17
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
SN54LVC257A 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN54LVC257AJ | ACTIVE | -55 to 125 | 15.25 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
| SNJ54LVC257AJ | ACTIVE | -55 to 125 | 12.46 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
| SNJ54LVC257AW | ACTIVE | -55 to 125 | 18.57 | 1ku | CFP (W) | 16 | 1 | TUBE |
SN54LVC257A 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN54LVC257AJ | TBD | A42 | N/A for Pkg Type | SN54LVC257AJ | SN54LVC257AJ |
| SNJ54LVC257AJ | TBD | A42 | N/A for Pkg Type | SNJ54LVC257AJ | SNJ54LVC257AJ |
| SNJ54LVC257AW | TBD | A42 | N/A for Pkg Type | SNJ54LVC257AW | SNJ54LVC257AW |
SN54LVC257A 应用技术支持与电子电路设计开发资源下载
- SN54LVC257A 数据资料 dataSheet 下载.PDF
- TI 德州仪器MSI 功能产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
