SN54S139 双路 2 线路至 4 线路解码器/多路解复用器
These Schottky-clamped TTL MSI circuits are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast-enable circuit, the delay times of these decoders and the enable time of the memory are usually less than the typical access time of the memory. This means that the effective system delay introduced by the Schottky-clamped system decoder is negligible.
The circuit comprises two individual two-line to four-line decoders in a single package. The active-low enable input can be used as a data line in demultiplexing applications
| SN54S139 | |
| Rating | Military |
| Technology Family | S |
SN54S139 特性
- Designed Specifically for High-Speed:
- Memory Decoders
- Data Transmission Systems
- Two Fully Independent 2- to 4-Line Decoders/Demultiplexers
- Schottky clamped for High Performance
SN54S139 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SNJ54S139FK | ACTIVE | -55 to 125 | 11.77 | 1ku | LCCC (FK) | 20 | 1 | TUBE | |
| SNJ54S139J | ACTIVE | -55 to 125 | 2.49 | 1ku | CDIP (J) | 16 | 1 | TUBE | |
| SNJ54S139W | ACTIVE | -55 to 125 | 12.36 | 1ku | CFP (W) | 16 | 1 | TUBE |
SN54S139 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SNJ54S139FK | TBD | POST-PLATE | N/A for Pkg Type | SNJ54S139FK | SNJ54S139FK |
| SNJ54S139J | TBD | A42 | N/A for Pkg Type | SNJ54S139J | SNJ54S139J |
| SNJ54S139W | TBD | A42 | N/A for Pkg Type | SNJ54S139W | SNJ54S139W |
SN54S139 应用技术支持与电子电路设计开发资源下载
- SN54S139 数据资料 dataSheet 下载.PDF
- TI 德州仪器MSI 功能产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
