SN54S280 9 位奇/偶校验发生器/检测器
These universal, monolithic, nine-bit parity generators/checkers utilize Schottky-clamped TTL high-performance circuitry and feature odd/even outputs to facilitate operation of either odd or even parity application. The word-length capability is easily expanded by cascading as shown under typical application data.
Series 54LS/74LS and Series 54S/74S parity generators/checkers offer the designer a trade-off between reduced power consumption and high performance. These devices can be used to upgrade the performance of most systems utilizing the '180 parity generator/checker. Although the 'LS280 and 'S280 are implemented without expander inputs, the corresponding function is provided by the availability of an input at pin 4 and the absence of any internal connection at pin 3
| SN54S280 | |
| Rating | Military |
| Technology Family | S |
SN54S280 特性
- Generates Either Odd or Even Parity for Nine Data Lines
- Cascadable for n-Bits
- Can Be Used to Upgrade Existing Systems using MSI Parity Circuits
- Typical Data-to-Output Delay of Only 14 ns for 'S280 and 33 ns for 'LS280
- Typical Power Dissipation:
- 'LS280 … 80 mW
- 'S280 … 335 mW
SN54S280 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN54S280J | ACTIVE | -55 to 125 | 4.38 | 1ku | CDIP (J) | 14 | 1 | TUBE | |
| SNJ54S280FK | ACTIVE | -55 to 125 | 12.33 | 1ku | LCCC (FK) | 20 | 1 | TUBE | |
| SNJ54S280J | ACTIVE | -55 to 125 | 5.15 | 1ku | CDIP (J) | 14 | 1 | TUBE | |
| SNJ54S280W | ACTIVE | -55 to 125 | 14.61 | 1ku | CFP (W) | 14 | 1 | TUBE |
SN54S280 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN54S280J | TBD | A42 | N/A for Pkg Type | SN54S280J | SN54S280J |
| SNJ54S280FK | TBD | POST-PLATE | N/A for Pkg Type | SNJ54S280FK | SNJ54S280FK |
| SNJ54S280J | TBD | A42 | N/A for Pkg Type | SNJ54S280J | SNJ54S280J |
| SNJ54S280W | TBD | A42 | N/A for Pkg Type | SNJ54S280W | SNJ54S280W |
SN54S280 应用技术支持与电子电路设计开发资源下载
- SN54S280 数据资料 dataSheet 下载.PDF
- TI 德州仪器MSI 功能产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
