CD74HC137 具有地址锁存器的高速 CMOS 逻辑 3 至 8 线解码器/多路解复用器
The CD74HC137, CD74HCT137, ’HC237, and CD74HCT237 are high speed silicon gate CMOS decoders well suited to memory address decoding or data routing applications. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic.
Both circuits have three binary select inputs (A0, A1 and A2) that can be latched by an active High Latch Enable (LE) signal to isolate the outputs from select-input changes. A "Low" LE makes the output transparent to the input and the circuit functions as a one-of-eight decoder. Two Output Enable inputs (OE\1 and OE0) are provided to simplify cascading and to facilitate demultiplexing. The demultiplexing function is accomplished by using the A0, A1, A2 inputs to select the desired output and using one of the other Output Enable inputs as the data input while holding the other Output Enable input in its active state
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CD74HC137 |
| Rating |
Catalog |
| Technology Family |
HC |
CD74HC137 特性
- Select One of Eight Data Outputs
- Active Low for CD74HC137 and CD74HCT137
- Active High for ’HC237 and CD74HCT237
- I/O Port or Memory Selector
- Two Enable Inputs to Simplify Cascading
- Typical Propagation Delay of 13ns at VCC = 5V, 15pF, TA = 25°C (CD74HC237)
- Fanout (Over Temperature Range)
- Standard Outputs. . . . 10 LSTTL Loads
- Bus Driver Outputs. . . . 15 LSTTL Loads
- Wide Operating Temperature Range . . . –55°C to 125°C
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30%, of VCC at VCC = 5V
- HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il
1µA at VOL, VOH
CD74HC137 芯片订购指南
| 器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| CD74HC137E |
ACTIVE |
-55 to 125 |
0.34 | 1ku |
PDIP (N) | 16 |
25 | TUBE |
|
| CD74HC137EE4 |
ACTIVE |
-55 to 125 |
0.34 | 1ku |
PDIP (N) | 16 |
25 | TUBE |
|
CD74HC137 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| CD74HC137E |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
CD74HC137E |
CD74HC137E |
| CD74HC137EE4 |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
CD74HC137EE4 |
CD74HC137EE4 |
CD74HC137 应用技术支持与电子电路设计开发资源下载
- CD74HC137 数据资料 dataSheet 下载.PDF
- TI 德州仪器MSI 功能产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
