CD74HCT4060 带振荡器的高速 CMOS 逻辑 14 级二进制计数器
The ’HC4060 and ’HCT4060 each consist of an oscillator section and 14 ripple-carry binary counter stages. The oscillator configuration allows design of either RC or crystal oscillator circuits. A Master Reset input is provided which resets the counter to the all-0’s state and disables the oscillator. A high level on the MR line accomplishes the reset function. All counter stages are master-slave flip-flops. The state of the counter is advanced one step in binary order on the negative transition of O). All inputs and outputs are buffered. Schmitt trigger action on the input-pulse-line permits unlimited rise and fall times.
In order to achieve a symmetrical waveform in the oscillator section the HCT4060 input pulse switch points are the same as in the HC4060; only the MR input in the HCT4060 has TTL switching levels
CD74HCT4060 特性
- Onboard Oscillator
- Common Reset
- Negative Edge Clocking
- Fanout (Over Temperature Range)
- Standard Outputs . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . 15 LSTTL Loads
- Wide Operating Temperature Range . . . –55°C to 125°C
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
- HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, Il 1µA at VOL, VOH
CD74HCT4060 芯片订购指南
器件 |
状态 |
温度 |
价格 |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
CD74HCT4060E |
ACTIVE |
-55 to 125 |
0.39 | 1ku |
PDIP (N) | 16 |
25 | TUBE |
|
CD74HCT4060EE4 |
ACTIVE |
-55 to 125 |
0.39 | 1ku |
PDIP (N) | 16 |
25 | TUBE |
|
CD74HCT4060M |
ACTIVE |
-55 to 125 |
0.42 | 1ku |
SOIC (DW) | 16 |
40 | TUBE |
|
CD74HCT4060M96 |
ACTIVE |
-55 to 125 |
0.35 | 1ku |
SOIC (DW) | 16 |
2500 | LARGE T&R |
|
CD74HCT4060M96E4 |
ACTIVE |
-55 to 125 |
0.35 | 1ku |
SOIC (DW) | 16 |
2500 | LARGE T&R |
|
CD74HCT4060M96G4 |
ACTIVE |
-55 to 125 |
0.35 | 1ku |
SOIC (DW) | 16 |
2500 | LARGE T&R |
|
CD74HCT4060ME4 |
ACTIVE |
-55 to 125 |
0.42 | 1ku |
SOIC (DW) | 16 |
40 | TUBE |
|
CD74HCT4060MG4 |
ACTIVE |
-55 to 125 |
0.42 | 1ku |
SOIC (DW) | 16 |
40 | TUBE |
|
CD74HCT4060 质量与无铅数据
器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
CD74HCT4060E |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
CD74HCT4060E |
CD74HCT4060E |
CD74HCT4060EE4 |
Pb-Free (RoHS) |
CU NIPDAU |
N/A for Pkg Type |
CD74HCT4060EE4 |
CD74HCT4060EE4 |
CD74HCT4060M |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HCT4060M |
CD74HCT4060M |
CD74HCT4060M96 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HCT4060M96 |
CD74HCT4060M96 |
CD74HCT4060M96E4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HCT4060M96E4 |
CD74HCT4060M96E4 |
CD74HCT4060M96G4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HCT4060M96G4 |
CD74HCT4060M96G4 |
CD74HCT4060ME4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HCT4060ME4 |
CD74HCT4060ME4 |
CD74HCT4060MG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
CD74HCT4060MG4 |
CD74HCT4060MG4 |
CD74HCT4060 应用技术支持与电子电路设计开发资源下载
- CD74HCT4060 数据资料 dataSheet 下载.PDF
- TI 德州仪器MSI 功能产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)