CD74HCT4514 带输入锁存器的高速 CMOS 逻辑 4 至 16 线路解码器/多路解复用器
The CD74HCT4514 and CD74HCT4515 are high-speed silicon-gate devices consisting of a 4-bit strobed latch and a 4-line to 16-line decoder. The selected output is enabled by a low on the enable (E)\ input. A high on E\ inhibits selection of any output. Demultiplexing is accomplished by using E\ as the data input and the select inputs (A0–A3) as addresses. E\ also serves as a chip select when these devices are cascaded.
When Latch Enable (LE\) is high the output follows changes in the inputs (see truth table). When LE is low the output is isolated from changes in the input and remains at the level (high for the 4514, low for the 4515) it had before the latches were enabled. These devices, enhanced versions of the equivalent CMOS types, can drive 10 LSTTL loads
| CD74HCT4514 | |
| Rating | Catalog |
| Technology Family | HCT |
CD74HCT4514 特性
- Multifunction Capability
- Binary to 1-of-16 Decoder
- 1-to-16 Line Demultiplexer
- Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . 15 LSTTL Loads
- Wide Operating Temperature Range . . . -55°C to 125°C
- Balanced Propagation Delay and Transition Times
- Significant Power Reduction Compared to LSTTL Logic ICs
- HC Types
- 2V to 6V Operation
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5V
CD74HCT4514 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| CD74HCT4514E | ACTIVE | -55 to 125 | 0.34 | 1ku | PDIP (N) | 24 | 25 | TUBE | |
| CD74HCT4514EE4 | ACTIVE | -55 to 125 | 0.34 | 1ku | PDIP (N) | 24 | 25 | TUBE |
CD74HCT4514 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| CD74HCT4514E | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | CD74HCT4514E | CD74HCT4514E |
| CD74HCT4514EE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | CD74HCT4514EE4 | CD74HCT4514EE4 |
CD74HCT4514 应用技术支持与电子电路设计开发资源下载
- CD74HCT4514 数据资料 dataSheet 下载.PDF
- TI 德州仪器MSI 功能产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
