SN74ABT16833 双路 8 位至 9 位奇偶校验总线收发器
SN74ABT16833 描述
The 'ABT16833 consist of two noninverting 8-bit to 9-bit parity bus transceivers and are designed for communication between data buses. For each transceiver, when data is transmitted from the A bus to the B bus, an odd-parity bit is generated and output on the parity I/O pin (1PARITY or 2PARITY). When data is transmitted from the B bus to the A bus, 1PARITY (or 2PARITY) is configured as an input and combined with the B-input data to generate an active-low error flag if odd parity is not detected.
The error (1
or 2) output is configured as an open-collector output. The B-to-A parity-error flag is clocked into 1 (or 2) on the low-to-high transition of the clock (1CLK or 2CLK) input. 1 (or 2) is cleared (set high) by taking the clear (1
or 2) input low
| SN74ABT16833 | |
| Voltage Nodes(V) | 5 |
| Vcc range(V) | 4.5 to 5.5 |
| Input Level | TTL |
| Output Level | TTL |
| Output Drive(mA) | -32/64 |
| No. of Outputs | 16 |
| Logic | True |
| Static Current | 19 |
| tpd max(ns) | 4.3 |
| Rating | Catalog |
| Technology Family | ABT |
SN74ABT16833 特性
- Members of the Texas Instruments WidebusTM Family
- State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
- Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
- Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C
- Distributed VCC and GND Pin Configuration Minimizes High-Speed Switching Noise
- Flow-Through Architecture Optimizes PCB Layout
- High-Drive Outputs (-32-mA IOH, 64-mA IOL)
- Parity-Error Flag With Parity Generator/Checker
- Register for Storage of Parity-Error Flag
- Package Options Include Plastic 300-mil Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings
SN74ABT16833 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74ABT16833DL | ACTIVE | -40 to 85 | 17.10 | 1ku | SSOP (DL) | 56 | 20 | TUBE | ABT16833 |
| SN74ABT16833DLR | ACTIVE | -40 to 85 | 14.25 | 1ku | SSOP (DL) | 56 | 1000 | LARGE T&R | ABT16833 |
SN74ABT16833 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74ABT16833DL | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ABT16833DL | SN74ABT16833DL |
| SN74ABT16833DLR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ABT16833DLR | SN74ABT16833DLR |
SN74ABT16833 应用技术支持与电子电路设计开发资源下载
- SN74ABT16833 数据资料 dataSheet 下载.PDF
- TI 德州仪器缓冲器、驱动器/收发器产品选型与价格 . xls
- CMOS 非缓冲反向器在振荡器电路中的使用 (PDF 951 KB)
- Semiconductor Packing Methodology (PDF 3005 KB)
- 逻辑产品选择指南 2006/2007 （修订版 Z）(4462KB)
- 标准线性和逻辑产品 5 分钟指南 (786KB)
- 了解和解释标准逻辑数据表
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
