SN74ABT18640 具有 18 位反向总线收发器的扫描测试设备
The 'ABT18640 scan test devices with 18-bit inverting bus transceivers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Standard 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface.
In the normal mode, these devices are 18-bit inverting bus transceivers. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells.
| SN74ABT18640 | |
| Voltage Nodes(V) | 5 |
| Vcc range(V) | 4.5 to 5.5 |
| Input Level | TTL |
| Logic | Inv |
| No. of Outputs | 18 |
| Output Drive(mA) | -32/64 |
| tpd max(ns) | 5.4 |
| Output Level | TTL |
| Static Current | 21.5 |
| Rating | Catalog |
| Technology Family | ABT |
SN74ABT18640 特性
- Members of the Texas Instruments SCOPETM Family of Testability Products
- Members of the Texas Instruments WidebusTM Family
- Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
- SCOPETM Instruction Set
- IEEE Standard 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
- Parallel-Signature Analysis at Inputs
- Pseudo-Random Pattern Generation From Outputs
- Sample Inputs/Toggle Outputs
- Binary Count From Outputs
- Device Identification
- Even-Parity Opcodes
- State-of-the-Art EPIC-IIBTM BiCMOS Design Significantly Reduces Power Dissipation
- Packaged in Plastic Shrink Small-Outline (DL) and Thin Shrink Small-Outline (DGG) Packages and 380-mil Fine-Pitch Ceramic Flat (WD) Packages
SN74ABT18640 芯片订购指南
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| 74ABT18640DGGRE4 | ACTIVE | -40 to 85 | 13.42 | 1ku | TSSOP (DGG) | 56 | 2000 | LARGE T&R | |
| 74ABT18640DGGRG4 | ACTIVE | -40 to 85 | 13.42 | 1ku | TSSOP (DGG) | 56 | 2000 | LARGE T&R | |
| SN74ABT18640DGGR | ACTIVE | -40 to 85 | 13.42 | 1ku | TSSOP (DGG) | 56 | 2000 | LARGE T&R | |
| SN74ABT18640DL | ACTIVE | -40 to 85 | 13.42 | 1ku | SSOP (DL) | 56 | 20 | TUBE | |
| SN74ABT18640DLG4 | ACTIVE | -40 to 85 | 13.42 | 1ku | SSOP (DL) | 56 | 20 | TUBE |
SN74ABT18640 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| 74ABT18640DGGRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ABT18640DGGRE4 | 74ABT18640DGGRE4 |
| 74ABT18640DGGRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | 74ABT18640DGGRG4 | 74ABT18640DGGRG4 |
| SN74ABT18640DGGR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ABT18640DGGR | SN74ABT18640DGGR |
| SN74ABT18640DL | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ABT18640DL | SN74ABT18640DL |
| SN74ABT18640DLG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ABT18640DLG4 | SN74ABT18640DLG4 |
SN74ABT18640 应用技术支持与电子电路设计开发资源下载
- SN74ABT18640 数据资料 dataSheet 下载.PDF
- TI 德州仪器特殊逻辑产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
