The 'ABT657A transceivers have eight noninverting buffers with parity-generator/ checker circuits and control signals. The transmit/receive (T/R\) input determines the direction of data flow. When T/R\ is high, data flows from the A port to the B port (transmit mode); when T/R\ is low, data flows from the B port to the A port (receive mode). When the output-enable (OE\) input is high, both the A and B ports are in the high-impedance state.
Odd or even parity is selected by a logic high or low level on the ODD/EVEN\ input. PARITY carries the parity-bit value; it is an output from the parity generator/checker in the transmit mode and an input to the parity generator/checker in the receive mode.
In the transmit mode, after the A bus is polled to determine the number of high bits, PARITY is set to the logic level that maintains the parity sense selected by the level at ODD/EVEN
| SN74ABT657A | |
| Voltage Nodes(V) | 5 |
| Vcc range(V) | 4.5 to 5.5 |
| Input Level | TTL |
| Output Level | TTL |
| Output Drive(mA) | -32/64 |
| No. of Outputs | 8 |
| Logic | True |
| Static Current | 20.12 |
| tpd max(ns) | 4.6 |
| Rating | Catalog |
| Technology Family | ABT |
| 器件 | 状态 | 温度 | 价格（美元） | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74ABT657ADW | ACTIVE | -40 to 85 | 1.80 | 1ku | SOIC (DW) | 24 | 25 | TUBE | ABT657A |
| SN74ABT657ADWE4 | ACTIVE | -40 to 85 | 1.80 | 1ku | SOIC (DW) | 24 | 25 | TUBE | ABT657A |
| SN74ABT657ADWG4 | ACTIVE | -40 to 85 | 1.80 | 1ku | SOIC (DW) | 24 | 25 | TUBE | ABT657A |
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74ABT657ADW | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ABT657ADW | SN74ABT657ADW |
| SN74ABT657ADWE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ABT657ADWE4 | SN74ABT657ADWE4 |
| SN74ABT657ADWG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74ABT657ADWG4 | SN74ABT657ADWG4 |
