SN74AS286 具有总线驱动器奇偶校验 I/O 端口的 9 位奇偶校验发生器/校验器
The SN54AS286 and SN74AS286 universal 9-bit parity generators/checkers feature a local output for parity checking and a 48-mA bus-driving
parity input/output (I/O) port for parity generation/checking. The word-length capability is easily expanded by cascading.
The transmit () control input is implemented specifically to accommodate cascading. When is low, the parity tree is disabled and PARITY ERROR remains at a high logic level regardless of the input levels. When is high, the parity tree is enabled. PARITY ERROR indicates a parity error when either an even number of inputs (A-I) are high and PARITY I/O is forced to a low logic level, or when an odd number of inputs are high and PARITY I/O is forced to a high logic level
| SN74AS286 | |
| Rating | Catalog |
| Technology Family | AS |
SN74AS286 特性
- Generate Either Odd or Even Parity forNine Data Lines
- Cascadable for n-Bit Parity
- Direct Bus Connection for Parity Generation or Checking by Using the Parity I/O Port
- Glitch-Free Bus During Power Up/Down
- Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs
SN74AS286 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74AS286E | ACTIVE | -55 to 125 | 0.60 | 1ku | PDIP (N) | 14 | 25 | TUBE | |
| SN74AS286EE4 | ACTIVE | -55 to 125 | 0.60 | 1ku | PDIP (N) | 14 | 25 | TUBE | |
| SN74AS286D | ACTIVE | -55 to 125 | 0.65 | 1ku | SOIC (D) | 14 | 50 | TUBE | |
| SN74AS286DR | ACTIVE | -55 to 125 | 0.55 | 1ku | SOIC (D) | 14 | 2500 | LARGE T&R | |
| SN74AS286DRE4 | ACTIVE | -55 to 125 | 0.55 | 1ku | SOIC (D) | 14 | 2500 | LARGE T&R | |
| SN74AS286DRG4 | ACTIVE | -55 to 125 | 0.55 | 1ku | SOIC (D) | 14 | 2500 | LARGE T&R | |
| SN74AS286DE4 | ACTIVE | -55 to 125 | 0.65 | 1ku | SOIC (D) | 14 | 50 | TUBE | |
| SN74AS286DG4 | ACTIVE | -55 to 125 | 0.65 | 1ku | SOIC (D) | 14 | 50 | TUBE |
SN74AS286 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74AS286E | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74AS286E | SN74AS286E |
| SN74AS286EE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74AS286EE4 | SN74AS286EE4 |
| SN74AS286D | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AS286D | SN74AS286D |
| SN74AS286DR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AS286DR | SN74AS286DR |
| SN74AS286DRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AS286DRE4 | SN74AS286DRE4 |
| SN74AS286DRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AS286DRG4 | SN74AS286DRG4 |
| SN74AS286DE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AS286DE4 | SN74AS286DE4 |
| SN74AS286DG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AS286DG4 | SN74AS286DG4 |
SN74AS286 应用技术支持与电子电路设计开发资源下载
- SN74AS286 数据资料 dataSheet 下载.PDF
- TI 德州仪器MSI 功能产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
