SN74AS885 8 位幅度比较器
These advanced Schottky devices are capable of performing high-speed arithmetic or logic comparisons on two 8-bit binary or two's complement words. Two fully decoded decisions about words P and Q are externally available at two outputs. These devices are fully expandable to any number of bits without external gates. To compare words of longer lengths, the P > QOUT and P < QOUT outputs of a stage handling less significant bits can be connected to the P > QIN and P < QIN inputs of the next stage handling more significant bits. The cascading paths are implemented with only a two-gate-level delay to reduce overall comparison times for long words. Two alternative methods of cascading are shown in application information.
| SN74AS885 | |
| Rating | Military |
| Technology Family | AS |
SN74AS885 特性
- Latchable P-Input Ports With Power-Up Clear
- Choice of Logical or Arithmetic (Two's Complement) Comparison
- Data and PLE Inputs Utilize pnp Input Transistors to Reduce dc Loading Effects
- Approximately 35% Improvement in ac Performance Over Schottky TTL While Performing More Functions
- Cascadable to n Bits While Maintaining High Performance
- 10% Less Power Than STTL for an 8-Bit Comparison
- Package Options Include Plastic Small-Outline (DW) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs
SN74AS885 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74AS885DW | ACTIVE | 0 to 70 | 1.85 | 1ku | SOIC(DW) | 24 | 25 | TUBE | |
| SN74AS885DWE4 | ACTIVE | 0 to 70 | 1.85 | 1ku | SOIC(DW) | 24 | 25 | TUBE | |
| SN74AS885DWG4 | ACTIVE | 0 to 70 | 1.85 | 1ku | SOIC(DW) | 24 | 25 | TUBE | |
| SN74AS885DWR | ACTIVE | 0 to 70 | 1.55 | 1ku | SOIC(DW) | 24 | 2000 | LARGE T&R | |
| SN74AS885DWRE4 | ACTIVE | 0 to 70 | 1.55 | 1ku | SOIC(DW) | 24 | 2000 | LARGE T&R | |
| SN74AS885DWRG4 | ACTIVE | 0 to 70 | 1.55 | 1ku | SOIC(DW) | 24 | 2000 | LARGE T&R | |
| SN74AS885N | ACTIVE | 0 to 70 | 1.70 | 1ku | PDIP (N) | 24 | 20 | TUBE | |
| SN74AS885NE4 | ACTIVE | 0 to 70 | 1.70 | 1ku | PDIP (N) | 24 | 20 | TUBE |
SN74AS885 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74AS885DW | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AS885DW | SN74AS885DW |
| SN74AS885DWE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AS885DWE4 | SN74AS885DWE4 |
| SN74AS885DWG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AS885DWG4 | SN74AS885DWG4 |
| SN74AS885DWR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AS885DWR | SN74AS885DWR |
| SN74AS885DWRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AS885DWRE4 | SN74AS885DWRE4 |
| SN74AS885DWRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74AS885DWRG4 | SN74AS885DWRG4 |
| SN74AS885N | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74AS885N | SN74AS885N |
| SN74AS885NE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74AS885NE4 | SN74AS885NE4 |
SN74AS885 应用技术支持与电子电路设计开发资源下载
- SN74AS885 数据资料 dataSheet 下载.PDF
- TI 德州仪器MSI 功能产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
