SN74CBTK6800 具有预充电输出和有源钳位下冲电路的 10 位 FET 总线开关

The SN74CBTK6800 device provides ten bits of high-speed TTL-compatible bus switching. The low on-state resistance of the switch allows bidirectional connections to be made while adding near-zero propagation delay. The device also precharges the B port to a user-selectable bias voltage (BIASV) to minimize live-insertion noise.

The A and B ports have an active-clamp undershoot-protection circuit. When there is an undershoot, the active-clamp circuit is enabled and current from VCC is supplied to clamp the output, preventing the pass transistor from turning on.

The SN74CBTK6800 is organized as one 10-bit switch with a single enable (ON\) input. When ON\ is low, the switch is on, and port A is connected to port B. When ON\ is high, the switch between port A and port B is open

SN74CBTK6800
Voltage Nodes(V) 5  
Vcc range(V) 4.0 to 5.5  
No. of Bits 10  
Input Level TTL  
Output Level TTL  
ron(max)(ohms) 20  
Static Current(Max) 0.02  
tpd max(ns) 0.25  
Rating Catalog  
Technology Family CBT
SN74CBTK6800 特性
SN74CBTK6800 芯片订购指南
器件 状态 温度 价格 封装 | 引脚 封装数量 | 封装载体 丝印标记
SN74CBTK6800DWR ACTIVE -40 to 85 1.45 | 1ku SOIC (DW) | 24 2000 | LARGE T&R  
SN74CBTK6800DWRE4 ACTIVE -40 to 85 1.45 | 1ku SOIC (DW) | 24 2000 | LARGE T&R  
SN74CBTK6800DWRG4 ACTIVE -40 to 85 1.45 | 1ku SOIC (DW) | 24 2000 | LARGE T&R  
SN74CBTK6800 质量与无铅数据
器件 环保计划* 铅/焊球涂层 MSL 等级/回流焊峰 环保信息与无铅 (Pb-free) DPPM / MTBF / FIT 率
SN74CBTK6800DWR Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74CBTK6800DWR SN74CBTK6800DWR
SN74CBTK6800DWRE4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74CBTK6800DWRE4 SN74CBTK6800DWRE4
SN74CBTK6800DWRG4 Green (RoHS & no Sb/Br)  CU NIPDAU  Level-1-260C-UNLIM SN74CBTK6800DWRG4 SN74CBTK6800DWRG4
SN74CBTK6800 应用技术支持与电子电路设计开发资源下载
  1. SN74CBTK6800 数据资料 dataSheet 下载.PDF
  2. TI 德州仪器信号开关产品选型与价格 . xls
  3. Logic Guide 2009 (PDF 4263 KB)
  4. 防止模拟开关的额外功耗 (PDF 392 KB) (PDF 1305 KB)
  5. Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
  6. TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
  7. Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
  8. CMOS Power Consumption and CPD Calculation (PDF 89 KB)
  9. Designing With Logic (PDF 186 KB)
  10. Live Insertion (PDF 150 KB)
  11. Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
  12. Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
  13. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  14. LOGIC Pocket Data Book (PDF 6001 KB)
  15. HiRel Unitrode Power Management Brochure (PDF 206 KB)
  16. Logic Cross-Reference (PDF 2938 KB)