SN74CBTLV3857 具有内部下拉电阻的低电压 10 位 FET 总线开关
This 10-bit FET bus switch is designed for 3-V to 3.6-V VCC operation and SSTL_2 output-enable (OE\) input levels.
When OE\ is low, the 10-bit bus switch is on, and port A is connected to port B. When OE\ is high, the switch is open, and the high-impedance state exists between the two ports. There are 10-k
pulldown resistors to ground on the B port.
The FET switch on-state resistance is designed to replace the series terminating resistor in the SSTL_2 data path.
This device is fully specified for partial-power-down applications using Ioff. The Ioff feature ensures that damaging current will not backflow through the device when it is powered down. The device has isolation during power off
| SN74CBTLV3857 | |
| Voltage Nodes(V) | 3.3, 2.5 |
| Vcc range(V) | 3.0 to 3.6 |
| No. of Bits | 10 |
| Input Level | LVTTL |
| ron(max)(ohms) | 8 |
| Static Current | 0.025 |
| tpd max(ns) | 0.25 |
| Rating | Catalog |
| Technology Family | CBTLV |
SN74CBTLV3857 特性
- Enable Signal Is SSTL_2 Compatible
- Flow-Through Architecture Optimizes PCB Layout
- Designed for Use With 200 Mbit/s Double Data-Rate (DDR) SDRAM Applications
- Switch On-State Resistance Is Designed to Eliminate Series Resistor to DDR SDRAM
- Internal 10-k Pulldown Resistors to Ground on B Port
- Internal 50-k Pullup Resistor on Output-Enable Input
- Rail-to-Rail Switching on Data I/O Ports
- Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
SN74CBTLV3857 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74CBTLV3857DW | ACTIVE | -40 to 85 | 0.65 | 1ku | SOIC(DW) | 24 | 50 | TUBE | |
| SN74CBTLV3857DWE4 | ACTIVE | -40 to 85 | 0.65 | 1ku | SOIC(DW) | 24 | 50 | TUBE | |
| SN74CBTLV3857DWG4 | ACTIVE | -40 to 85 | 0.65 | 1ku | SOIC(DW) | 24 | 50 | TUBE | |
| SN74CBTLV3857DWR | ACTIVE | -40 to 85 | 0.55 | 1ku | SOIC(DW) | 24 | 2500 | LARGE T&R | |
| SN74CBTLV3857DWRE4 | ACTIVE | -40 to 85 | 0.55 | 1ku | SOIC(DW) | 24 | 2500 | LARGE T&R | |
| SN74CBTLV3857DWRG4 | ACTIVE | -40 to 85 | 0.55 | 1ku | SOIC(DW) | 24 | 2500 | LARGE T&R |
SN74CBTLV3857 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74CBTLV3857DW | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74CBTLV3857DW | SN74CBTLV3857DW |
| SN74CBTLV3857DWE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74CBTLV3857DWE4 | SN74CBTLV3857DWE4 |
| SN74CBTLV3857DWG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74CBTLV3857DWG4 | SN74CBTLV3857DWG4 |
| SN74CBTLV3857DWR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74CBTLV3857DWR | SN74CBTLV3857DWR |
| SN74CBTLV3857DWRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74CBTLV3857DWRE4 | SN74CBTLV3857DWRE4 |
| SN74CBTLV3857DWRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74CBTLV3857DWRG4 | SN74CBTLV3857DWRG4 |
SN74CBTLV3857 应用技术支持与电子电路设计开发资源下载
- SN74CBTLV3857 数据资料 dataSheet 下载.PDF
- TI 德州仪器信号开关产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- 防止模拟开关的额外功耗 (PDF 392 KB) (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
