SN74GTLPH16912 18 位 LVTTL 到 GTLP 通用总线收发器
The SN74GTLPH16912 is a 17-bit UBT™ transceiver that provides LVTTL-to-GTL/GTL+ and GTL/GTL+-to-LVTTL signal-level translation. Combined D-type flip-flops and D-type latches allow for transparent, latched, clocked, and clocked-enabled modes of data transfer identical to the '16601 function. Additionally, this device provides for a copy of CLKAB at GTL/GTL+ signal levels (CLKOUT) and conversion of a GTL/GTL+ clock to LVTTL logic levels (CLKIN). This device provides an interface between cards operating at LVTTL logic levels and a backplane operating at GTL/GTL+ signal levels. Higher-speed operation is a direct result of the reduced output swing (<1 V), reduced input threshold levels, and OEC™ circuitry.
|
SN74GTLPH16912 |
| Voltage Nodes(V) |
5, 3.3 |
| A Side |
LVTTL |
| B Side |
GTL |
| Fclock(Max)(MHz) |
95 |
| Bus Drive(ma) |
-32/64 |
| No. of Bits |
17 |
| th(ns) |
3.5 |
| tsu(ns) |
2.7 |
| Static Current |
5 |
| Rating |
Catalog |
| Technology Family |
GTL |
SN74GTLPH16912 特性
- Member of Texas Instruments' Widebus™ Family
- UBT™ Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, Clocked, or Clock-Enabled Modes
- OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference
- GTL Buffered CLKAB Signal (CLKOUT)
- Translates Between GTL/GTL+ Signal Levels and LVTTL Logic Levels
- Supports Mixed-Mode (3.3 V and 5 V) Signal Operation on A-Port and Control Inputs
- Equivalent to \x9216601 Function
- Ioff Supports Partial-Power-Down Mode Operation
- Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors on A Port
- Distributed VCC and GND Pins Minimize High-Speed Switching Noise
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
SN74GTLPH16912 芯片订购指南
| 器件 |
状态 |
温度 |
价格（美元） |
封装 | 引脚 |
封装数量 | 封装载体 |
丝印标记 |
| 74GTL16616DGGRE4 |
ACTIVE |
-40 to 85 |
12.55 | 1ku |
TSSOP (DGG) | 56 |
2000 | LARGE T&R |
|
| 74GTL16616DGGRG4 |
ACTIVE |
-40 to 85 |
12.55 | 1ku |
TSSOP (DGG) | 56 |
2000 | LARGE T&R |
|
| SN74GTLPH16912DGGR |
ACTIVE |
-40 to 85 |
12.55 | 1ku |
TSSOP (DGG) | 56 |
2000 | LARGE T&R |
|
| SN74GTLPH16912DLR |
ACTIVE |
-40 to 85 |
13.80 | 1ku |
SSOP (DL) | 56 |
1000 | LARGE T&R |
|
| SN74GTLPH16912DLRG4 |
ACTIVE |
-40 to 85 |
13.80 | 1ku |
SSOP (DL) | 56 |
1000 | LARGE T&R |
|
SN74GTLPH16912 质量与无铅数据
| 器件 |
环保计划* |
铅/焊球涂层 |
MSL 等级/回流焊峰 |
环保信息与无铅 (Pb-free) |
DPPM / MTBF / FIT 率 |
| 74GTL16616DGGRE4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
74GTL16616DGGRE4 |
74GTL16616DGGRE4 |
| 74GTL16616DGGRG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
74GTL16616DGGRG4 |
74GTL16616DGGRG4 |
| SN74GTLPH16912DGGR |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74GTLPH16912DGGR |
SN74GTLPH16912DGGR |
| SN74GTLPH16912DLR |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74GTLPH16912DLR |
SN74GTLPH16912DLR |
| SN74GTLPH16912DLRG4 |
Green (RoHS & no Sb/Br) |
CU NIPDAU |
Level-1-260C-UNLIM |
SN74GTLPH16912DLRG4 |
SN74GTLPH16912DLRG4 |
SN74GTLPH16912 应用技术支持与电子电路设计开发资源下载
- SN74GTLPH16912 数据资料 dataSheet 下载.PDF
- TI 德州仪器特殊逻辑产品选型与价格 . xls
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
