SN74LV10A 三路 3 输入正与非门
These triple 3-input positive-NAND gates are \designed for 2-V to 5.5-V VCC operation.
The 'LV10A devices perform the Boolean function Y = (A • B • C)\ or Y = A\ + B\ + C\ in positive logic.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down
| SN74LV10A | |
| Rating | Catalog |
| Technology Family | LV-A |
SN74LV10A 特性
- 2-V to 5.5-V VCC Operation
- Max tpd of 7 na at 5 V
- Typical VOLP (Output Ground Bounce)
<0.8 V at VCC, TA = 25°C - Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC, TA = 25°C - Ioff Supports Partial-Power-Down Mode Operation
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101
SN74LV10A 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74LV10AD | ACTIVE | -40 to 85 | 0.20 | 1ku | SOIC (D) | 14 | 50 | TUBE | 74LV10A |
| SN74LV10ADE4 | ACTIVE | -40 to 85 | 0.20 | 1ku | SOIC (D) | 14 | 50 | TUBE | 74LV10A |
| SN74LV10ADG4 | ACTIVE | -40 to 85 | 0.20 | 1ku | SOIC (D) | 14 | 50 | TUBE | 74LV10A |
| SN74LV10ADR | ACTIVE | 0 to 70 | 0.26 | 1ku | SOIC (D) | 14 | 2500 | LARGE T&R | 74LV10A |
| SN74LV10ADRE4 | ACTIVE | 0 to 70 | 0.26 | 1ku | SOIC (D) | 14 | 2500 | LARGE T&R | 74LV10A |
| SN74LV10ADRG4 | ACTIVE | 0 to 70 | 0.26 | 1ku | SOIC (D) | 14 | 2500 | LARGE T&R | 74LV10A |
| SN74LV10AN | ACTIVE | 0 to 70 | 0.95 | 1ku | PDIP (N) | 14 | 20 | TUBE | SN74LV10AN |
| SN74LV10ANE4 | ACTIVE | 0 to 70 | 0.95 | 1ku | PDIP (N) | 14 | 20 | TUBE | SN74LV10AN |
SN74LV10A 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74LV10AD | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV10AD | SN74LV10AD |
| SN74LV10ADE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV10ADE4 | SN74LV10ADE4 |
| SN74LV10ADG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV10ADG4 | SN74LV10ADG4 |
| SN74LV10ADR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV10ADR | SN74LV10ADR |
| SN74LV10ADRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV10ADRE4 | SN74LV10ADRE4 |
| SN74LV10ADRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV10ADRG4 | SN74LV10ADRG4 |
| SN74LV10AN | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74LV10AN | SN74LV10AN |
| SN74LV10ANE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74LV10ANE4 | SN74LV10ANE4 |
SN74LV10A 应用技术支持与电子电路设计开发资源下载
- SN74LV10A 数据资料 dataSheet 下载.PDF
- TI 德州仪器门电路产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
