SN74LV11A-EP 增强型产品三路 3 输入正与门
This triple 3-input positive-AND gate is designed for 2-V to 5.5-V VCC operation.
The SN74LV11A performs the Boolean function Y = A • B • C or Y = (A\ + B\ + C\)\ in positive logic.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down
| SN74LV11A-EP | |
| Rating | HiRel Enhanced Product |
| Technology Family | LV-A |
SN74LV11A-EP 特性
- Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
- Extended Temperature Performance of –40°C to 105°C
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product-Change Notification
- Qualification Pedigree
- 2-V to 5.5-V VCC Operation
- Typical VOLP (Output Ground Bounce)
<0.8 V at VCC= 3.3 V, TA = 25°C - Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C - Supports Mixed-Mode Voltage Operation on All Ports
- Ioff Supports Partial-Power-Down Mode Operation
SN74LV11A-EP 芯片订购指南
| 器件 | 状态 | 温度 | 价格 | 封装 | 引脚 | 封装数量 | 封装载体 | 丝印标记 |
| SN74LV11A-EPD | ACTIVE | -40 to 85 | 0.24 | 1ku | SOIC (D) | 14 | 50 | TUBE | |
| SN74LV11A-EPDE4 | ACTIVE | -40 to 85 | 0.24 | 1ku | SOIC (D) | 14 | 50 | TUBE | |
| SN74LV11A-EPDG4 | ACTIVE | -40 to 85 | 0.24 | 1ku | SOIC (D) | 14 | 50 | TUBE | |
| SN74LV11A-EPDR | ACTIVE | -40 to 85 | 0.20 | 1ku | SOIC (D) | 14 | 2500 | LARGE T&R | |
| SN74LV11A-EPDRE4 | ACTIVE | -40 to 85 | 0.20 | 1ku | SOIC (D) | 14 | 2500 | LARGE T&R | |
| SN74LV11A-EPDRG4 | ACTIVE | -40 to 85 | 0.20 | 1ku | SOIC (D) | 14 | 2500 | LARGE T&R | |
| SN74LV11A-EPN | ACTIVE | -40 to 85 | 0.22 | 1ku | PDIP (N) | 14 | 25 | TUBE | |
| SN74LV11A-EPNE4 | ACTIVE | -40 to 85 | 0.22 | 1ku | PDIP (N) | 14 | 25 | TUBE |
SN74LV11A-EP 质量与无铅数据
| 器件 | 环保计划* | 铅/焊球涂层 | MSL 等级/回流焊峰 | 环保信息与无铅 (Pb-free) | DPPM / MTBF / FIT 率 |
| SN74LV11A-EPD | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV11A-EPD | SN74LV11A-EPD |
| SN74LV11A-EPDE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV11A-EPDE4 | SN74LV11A-EPDE4 |
| SN74LV11A-EPDG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV11A-EPDG4 | SN74LV11A-EPDG4 |
| SN74LV11A-EPDR | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV11A-EPDR | SN74LV11A-EPDR |
| SN74LV11A-EPDRE4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV11A-EPDRE4 | SN74LV11A-EPDRE4 |
| SN74LV11A-EPDRG4 | Green (RoHS & no Sb/Br) | CU NIPDAU | Level-1-260C-UNLIM | SN74LV11A-EPDRG4 | SN74LV11A-EPDRG4 |
| SN74LV11A-EPN | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74LV11A-EPN | SN74LV11A-EPN |
| SN74LV11A-EPNE4 | Pb-Free (RoHS) | CU NIPDAU | N/A for Pkg Type | SN74LV11A-EPNE4 | SN74LV11A-EPNE4 |
SN74LV11A-EP 应用技术支持与电子电路设计开发资源下载
- SN74LV11A-EP 数据资料 dataSheet 下载.PDF
- TI 德州仪器门电路产品选型与价格 . xls
- Logic Guide 2009 (PDF 4263 KB)
- Shelf-Life Evaluation of Lead-Free Component Finishes (PDF 1305 KB)
- Understanding and Interpreting Standard-Logic Data Sheets (PDF 857 KB)
- TI IBIS File Creation, Validation, and Distribution Processes (PDF 380 KB)
- Implications of Slow or Floating CMOS Inputs (PDF 101 KB)
- CMOS Power Consumption and CPD Calculation (PDF 89 KB)
- Designing With Logic (PDF 186 KB)
- Live Insertion (PDF 150 KB)
- Input and Output Characteristics of Digital Integrated Circuits (PDF 1708 KB)
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc (PDF 43 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- LOGIC Pocket Data Book (PDF 6001 KB)
- HiRel Unitrode Power Management Brochure (PDF 206 KB)
- Logic Cross-Reference (PDF 2938 KB)
